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initial import

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Clifford Wolf 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
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tests/hana/test_simulation_always_23_test.v Normal file
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module MyCounter (clock, preset, updown, presetdata, counter);
input clock, preset, updown;
input [1: 0] presetdata;
output reg [1:0] counter;
always @(posedge clock)
if(preset)
counter <= presetdata;
else
if(updown)
counter <= counter + 1;
else
counter <= counter - 1;
endmodule