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initial import

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Clifford Wolf 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
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tests/hana/test_simulation_always_22_test.v Normal file
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@ -0,0 +1,7 @@
module inc(clock, counter);
input clock;
output reg [7:0] counter;
always @(posedge clock)
counter <= counter + 1;
endmodule