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Clifford Wolf 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
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tests/hana/test_intermout_exprs_varshift_test.v Normal file
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module test(vin0, vout0);
input [2:0] vin0;
output reg [7:0] vout0;
wire [7:0] myreg0, myreg1, myreg2;
integer i;
assign myreg0 = vout0 << vin0;
assign myreg1 = myreg2 >> i;
endmodule