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Clifford Wolf 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
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tests/hana/test_intermout_exprs_redand_test.v Normal file
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module test(output out, input [1:0] vin, output out1, input [3:0] vin1);
assign out = &vin;
assign out1 = &vin1;
endmodule