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initial import

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Clifford Wolf 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
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tests/hana/test_intermout_always_ff_8_test.v Normal file
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module NegEdgeClock(q, d, clk, reset);
input d, clk, reset;
output reg q;
always @(negedge clk or negedge reset)
if(!reset)
q <= 1'b0;
else
q <= d;
endmodule