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initial import

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Clifford Wolf 2013-01-05 11:13:26 +01:00
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tests/asicworld/code_verilog_tutorial_multiply.v Normal file
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module muliply (a,product);
input [3:0] a;
output [4:0] product;
wire [4:0] product;
assign product = a << 1;
endmodule