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initial import

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Clifford Wolf 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
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tests/asicworld/code_tidbits_reg_seq_example.v Normal file
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module reg_seq_example( clk, reset, d, q);
input clk, reset, d;
output q;
reg q;
wire clk, reset, d;
always @ (posedge clk or posedge reset)
if (reset) begin
q <= 1'b0;
end else begin
q <= d;
end
endmodule