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initial import

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Clifford Wolf 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
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tests/asicworld/code_tidbits_reg_combo_example.v Normal file
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module reg_combo_example( a, b, y);
input a, b;
output y;
reg y;
wire a, b;
always @ ( a or b)
begin
y = a & b;
end
endmodule