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initial import

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Clifford Wolf 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
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tests/asicworld/code_tidbits_nonblocking.v Normal file
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module nonblocking (clk,a,c);
input clk;
input a;
output c;
wire clk;
wire a;
reg c;
reg b;
always @ (posedge clk )
begin
b <= a;
c <= b;
end
endmodule