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initial import

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Clifford Wolf 2013-01-05 11:13:26 +01:00
commit 7764d0ba1d
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tests/asicworld/code_tidbits_asyn_reset.v Normal file
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module asyn_reset(clk,reset,a,c);
input clk;
input reset;
input a;
output c;
wire clk;
wire reset;
wire a;
reg c;
always @ (posedge clk or posedge reset)
if ( reset == 1'b1) begin
c <= 0;
end else begin
c <= a;
end
endmodule