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https://github.com/YosysHQ/yosys
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initial import
This commit is contained in:
Clifford Wolf
commit
7764d0ba1d
481 changed files with 54634 additions and 0 deletions
239
passes/opt/opt_rmunused.cc
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239
passes/opt/opt_rmunused.cc
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "opt_status.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/celltypes.h"
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <set>
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static CellTypes ct;
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static void rmunused_module_cells(RTLIL::Module *module)
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{
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SigMap assign_map(module);
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std::set<RTLIL::Cell*> queue, unused;
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SigSet<RTLIL::Cell*> wire2driver;
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for (auto &it : module->cells) {
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RTLIL::Cell *cell = it.second;
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for (auto &it2 : cell->connections) {
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if (!ct.cell_input(cell->type, it2.first)) {
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RTLIL::SigSpec sig = it2.second;
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assign_map.apply(sig);
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wire2driver.insert(sig, cell);
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}
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}
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if (cell->type == "$memwr")
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queue.insert(cell);
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unused.insert(cell);
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}
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for (auto &it : module->wires) {
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RTLIL::Wire *wire = it.second;
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if (wire->port_output) {
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std::set<RTLIL::Cell*> cell_list;
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RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
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assign_map.apply(sig);
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wire2driver.find(sig, cell_list);
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for (auto cell : cell_list)
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queue.insert(cell);
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}
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}
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while (queue.size() > 0)
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{
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std::set<RTLIL::Cell*> new_queue;
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for (auto cell : queue)
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unused.erase(cell);
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for (auto cell : queue) {
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for (auto &it : cell->connections) {
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if (!ct.cell_output(cell->type, it.first)) {
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std::set<RTLIL::Cell*> cell_list;
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RTLIL::SigSpec sig = it.second;
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assign_map.apply(sig);
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wire2driver.find(sig, cell_list);
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for (auto cell : cell_list) {
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if (unused.count(cell) > 0)
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new_queue.insert(cell);
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}
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}
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}
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}
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queue.swap(new_queue);
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}
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for (auto cell : unused) {
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log(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
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OPT_DID_SOMETHING = true;
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module->cells.erase(cell->name);
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delete cell;
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}
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}
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static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2)
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{
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assert(s1.width == 1);
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assert(s2.width == 1);
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assert(s1.chunks.size() == 1);
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assert(s2.chunks.size() == 1);
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RTLIL::Wire *w1 = s1.chunks[0].wire;
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RTLIL::Wire *w2 = s2.chunks[0].wire;
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if (w1 == NULL || w2 == NULL)
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return w2 == NULL;
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if (w1->port_input != w2->port_input)
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return w2->port_input;
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if (w1->name[0] != w2->name[0])
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return w2->name[0] == '\\';
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if (w1->attributes.size() != w2->attributes.size())
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return w2->attributes.size() > w1->attributes.size();
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return w2->name < w1->name;
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}
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static void rmunused_module_signals(RTLIL::Module *module)
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{
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SigMap assign_map(module);
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for (auto &it : module->wires) {
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RTLIL::Wire *wire = it.second;
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for (int i = 0; i < wire->width; i++) {
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RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, 1, i), s2 = assign_map(s1);
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if (!compare_signals(s1, s2))
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assign_map.add(s1);
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}
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}
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module->connections.clear();
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SigPool used_signals;
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SigPool used_signals_nodrivers;
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for (auto &it : module->cells) {
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RTLIL::Cell *cell = it.second;
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for (auto &it2 : cell->connections) {
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assign_map.apply(it2.second);
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used_signals.add(it2.second);
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if (!ct.cell_output(cell->type, it2.first))
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used_signals_nodrivers.add(it2.second);
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}
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}
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std::vector<RTLIL::Wire*> del_wires;
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for (auto &it : module->wires) {
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RTLIL::Wire *wire = it.second;
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if (wire->name[0] == '\\') {
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RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1;
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assign_map.apply(s2);
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if (!used_signals.check_any(s2) && wire->port_id == 0) {
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log(" removing unused non-port wire %s.\n", wire->name.c_str());
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del_wires.push_back(wire);
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} else {
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s1.expand();
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s2.expand();
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assert(s1.chunks.size() == s2.chunks.size());
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RTLIL::SigSig new_conn;
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for (size_t i = 0; i < s1.chunks.size(); i++)
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if (s1.chunks[i] != s2.chunks[i]) {
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new_conn.first.append(s1.chunks[i]);
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new_conn.second.append(s2.chunks[i]);
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}
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if (new_conn.first.width > 0) {
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new_conn.first.optimize();
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new_conn.second.optimize();
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module->connections.push_back(new_conn);
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}
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}
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} else {
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if (!used_signals.check_any(RTLIL::SigSpec(wire)))
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del_wires.push_back(wire);
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}
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RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire));
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if (!used_signals_nodrivers.check_any(sig)) {
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std::string unused_bits;
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sig.expand();
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for (size_t i = 0; i < sig.chunks.size(); i++) {
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if (sig.chunks[i].wire == NULL)
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continue;
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if (!used_signals_nodrivers.check_any(sig)) {
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if (!unused_bits.empty())
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unused_bits += " ";
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unused_bits += stringf("%zd", i);
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}
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}
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if (unused_bits.empty() || wire->port_id != 0)
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wire->attributes.erase("\\unused_bits");
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else
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wire->attributes["\\unused_bits"] = RTLIL::Const(unused_bits);
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} else {
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wire->attributes.erase("\\unused_bits");
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}
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}
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for (auto wire : del_wires) {
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module->wires.erase(wire->name);
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delete wire;
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}
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if (del_wires.size() > 0)
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log(" removed %zd unused temporary wires.\n", del_wires.size());
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}
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static void rmunused_module(RTLIL::Module *module)
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{
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log("Finding unused cells or wires in module %s..\n", module->name.c_str());
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rmunused_module_cells(module);
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rmunused_module_signals(module);
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}
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struct OptRmUnusedPass : public Pass {
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OptRmUnusedPass() : Pass("opt_rmunused") { }
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing OPT_RMUNUSED pass (remove unused cells and wires).\n");
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log_push();
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extra_args(args, 1, design);
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ct.setup_internals();
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ct.setup_internals_mem();
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ct.setup_stdcells();
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ct.setup_stdcells_mem();
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for (auto &mod_it : design->modules) {
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if (mod_it.second->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
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} else {
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rmunused_module(mod_it.second);
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}
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}
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ct.clear();
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log_pop();
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}
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} OptRmUnusedPass;
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