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https://github.com/YosysHQ/yosys
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initial import
This commit is contained in:
Clifford Wolf
commit
7764d0ba1d
481 changed files with 54634 additions and 0 deletions
334
passes/memory/memory_map.cc
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334
passes/memory/memory_map.cc
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <sstream>
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#include <set>
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#include <stdlib.h>
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#include <assert.h>
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static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
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{
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std::stringstream sstr;
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sstr << "$memory" << name << token1;
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if (i >= 0)
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sstr << "[" << i << "]";
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sstr << token2;
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if (j >= 0)
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sstr << "[" << j << "]";
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sstr << token3;
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if (k >= 0)
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sstr << "[" << k << "]";
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sstr << token4 << "$" << (RTLIL::autoidx++);
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return sstr.str();
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}
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static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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std::set<int> static_ports;
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std::map<int, RTLIL::SigSpec> static_cells_map;
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int mem_size = cell->parameters["\\SIZE"].as_int();
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int mem_width = cell->parameters["\\WIDTH"].as_int();
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int mem_offset = cell->parameters["\\OFFSET"].as_int();
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int mem_abits = cell->parameters["\\ABITS"].as_int();
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// delete unused memory cell
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if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) {
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module->cells.erase(cell->name);
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delete cell;
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return;
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}
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// all write ports must share the same clock
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RTLIL::SigSpec clocks = cell->connections["\\WR_CLK"];
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RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
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RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
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RTLIL::SigSpec refclock;
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RTLIL::State refclock_pol = RTLIL::State::Sx;
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for (int i = 0; i < clocks.width; i++) {
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RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i, 1);
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if (wr_en.is_fully_const() && wr_en.as_int() == 0) {
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static_ports.insert(i);
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continue;
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}
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if (clocks_en.bits[i] != RTLIL::State::S1) {
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RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(i*mem_abits, mem_abits);
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RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(i*mem_width, mem_width);
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if (wr_addr.is_fully_const()) {
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// FIXME: Actually we should check for wr_en.is_fully_const() also and
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// create a $adff cell with this ports wr_en input as reset pin when wr_en
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// is not a simple static 1.
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static_cells_map[wr_addr.as_int()] = wr_data;
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static_ports.insert(i);
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continue;
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}
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log("Not mapping memory cell %s in module %s (write port %d has no clock).\n",
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cell->name.c_str(), module->name.c_str(), i);
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return;
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}
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if (refclock.width == 0) {
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refclock = clocks.extract(i, 1);
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refclock_pol = clocks_pol.bits[i];
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}
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if (clocks.extract(i, 1) != refclock || clocks_pol.bits[i] != refclock_pol) {
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log("Not mapping memory cell %s in module %s (write clock %d is incompatible with other clocks).\n",
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cell->name.c_str(), module->name.c_str(), i);
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return;
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}
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}
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log("Mapping memory cell %s in module %s:\n", cell->name.c_str(), module->name.c_str());
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std::vector<RTLIL::SigSpec> data_reg_in;
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std::vector<RTLIL::SigSpec> data_reg_out;
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int count_static = 0;
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for (int i = 0; i < mem_size; i++)
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{
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if (static_cells_map.count(i) > 0)
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{
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data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem_width));
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data_reg_out.push_back(static_cells_map[i]);
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count_static++;
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}
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else
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{
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RTLIL::Cell *c = new RTLIL::Cell;
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c->name = genid(cell->name, "", i);
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c->type = "$dff";
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c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
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c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
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c->connections["\\CLK"] = clocks.extract(0, 1);
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module->cells[c->name] = c;
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RTLIL::Wire *w_in = new RTLIL::Wire;
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w_in->name = genid(cell->name, "", i, "$d");
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w_in->width = mem_width;
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module->wires[w_in->name] = w_in;
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data_reg_in.push_back(RTLIL::SigSpec(w_in));
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c->connections["\\D"] = data_reg_in.back();
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RTLIL::Wire *w_out = new RTLIL::Wire;
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w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].str.c_str(), i);
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if (module->wires.count(w_out->name) > 0)
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w_out->name = genid(cell->name, "", i, "$q");
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w_out->width = mem_width;
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w_out->start_offset = mem_offset;
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module->wires[w_out->name] = w_out;
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data_reg_out.push_back(RTLIL::SigSpec(w_out));
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c->connections["\\Q"] = data_reg_out.back();
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}
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}
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log(" created %d $dff cells and %d static cells of width %d.\n", mem_size-count_static, count_static, mem_width);
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int count_dff = 0, count_mux = 0, count_wrmux = 0;
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for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++)
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{
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RTLIL::SigSpec rd_addr = cell->connections["\\RD_ADDR"].extract(i*mem_abits, mem_abits);
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std::vector<RTLIL::SigSpec> rd_signals;
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rd_signals.push_back(cell->connections["\\RD_DATA"].extract(i*mem_width, mem_width));
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if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1)
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{
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#if 1
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RTLIL::Cell *c = new RTLIL::Cell;
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c->name = genid(cell->name, "$rdreg", i);
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c->type = "$dff";
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c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
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c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
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c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1);
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c->connections["\\D"] = rd_addr;
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module->cells[c->name] = c;
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count_dff++;
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RTLIL::Wire *w = new RTLIL::Wire;
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w->name = genid(cell->name, "$rdreg", i, "$q");
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w->width = mem_abits;
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module->wires[w->name] = w;
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c->connections["\\Q"] = RTLIL::SigSpec(w);
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rd_addr = RTLIL::SigSpec(w);
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#else
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RTLIL::Cell *c = new RTLIL::Cell;
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c->name = genid(cell->name, "$rdreg", i);
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c->type = "$dff";
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c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
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c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
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c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1);
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c->connections["\\Q"] = rd_signals.back();
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module->cells[c->name] = c;
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count_dff++;
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RTLIL::Wire *w = new RTLIL::Wire;
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w->name = genid(cell->name, "$rdreg", i, "$d");
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w->width = mem_width;
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module->wires[w->name] = w;
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rd_signals.clear();
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rd_signals.push_back(RTLIL::SigSpec(w));
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c->connections["\\D"] = rd_signals.back();
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#endif
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}
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for (int j = 0; j < mem_abits; j++)
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{
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std::vector<RTLIL::SigSpec> next_rd_signals;
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for (size_t k = 0; k < rd_signals.size(); k++)
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{
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RTLIL::Cell *c = new RTLIL::Cell;
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c->name = genid(cell->name, "$rdmux", i, "", j, "", k);
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c->type = "$mux";
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c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
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c->connections["\\Y"] = rd_signals[k];
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c->connections["\\S"] = rd_addr.extract(mem_abits-j-1, 1);
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module->cells[c->name] = c;
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count_mux++;
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RTLIL::Wire *w = new RTLIL::Wire;
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w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a");
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w->width = mem_width;
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module->wires[w->name] = w;
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c->connections["\\A"] = RTLIL::SigSpec(w);
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w = new RTLIL::Wire;
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w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b");
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w->width = mem_width;
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module->wires[w->name] = w;
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c->connections["\\B"] = RTLIL::SigSpec(w);
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next_rd_signals.push_back(c->connections["\\A"]);
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next_rd_signals.push_back(c->connections["\\B"]);
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}
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next_rd_signals.swap(rd_signals);
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}
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for (int j = 0; j < mem_size; j++)
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module->connections.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j]));
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}
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log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux);
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for (int i = 0; i < mem_size; i++)
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{
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if (static_cells_map.count(i) > 0)
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continue;
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RTLIL::SigSpec sig = data_reg_out[i];
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for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++)
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{
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RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(j*mem_abits, mem_abits);
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RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width);
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RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j, 1);
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RTLIL::Cell *c = new RTLIL::Cell;
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c->name = genid(cell->name, "$wreq", i, "", j);
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c->type = "$eq";
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c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
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c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"];
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c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"];
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c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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c->connections["\\A"] = RTLIL::SigSpec(i, mem_abits);
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c->connections["\\B"] = wr_addr;
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module->cells[c->name] = c;
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count_wrmux++;
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RTLIL::Wire *w = new RTLIL::Wire;
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w->name = genid(cell->name, "$wreq", i, "", j, "$y");
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module->wires[w->name] = w;
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c->connections["\\Y"] = RTLIL::SigSpec(w);
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c = new RTLIL::Cell;
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c->name = genid(cell->name, "$wren", i, "", j);
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c->type = "$and";
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c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
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c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
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c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
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c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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c->connections["\\A"] = RTLIL::SigSpec(w);
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c->connections["\\B"] = wr_en;
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module->cells[c->name] = c;
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w = new RTLIL::Wire;
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w->name = genid(cell->name, "$wren", i, "", j, "$y");
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module->wires[w->name] = w;
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c->connections["\\Y"] = RTLIL::SigSpec(w);
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c = new RTLIL::Cell;
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c->name = genid(cell->name, "$wrmux", i, "", j);
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c->type = "$mux";
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c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
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c->connections["\\A"] = sig;
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c->connections["\\B"] = wr_data;
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c->connections["\\S"] = RTLIL::SigSpec(w);
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module->cells[c->name] = c;
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w = new RTLIL::Wire;
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w->name = genid(cell->name, "$wrmux", i, "", j, "$y");
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w->width = mem_width;
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module->wires[w->name] = w;
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c->connections["\\Y"] = RTLIL::SigSpec(w);
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sig = RTLIL::SigSpec(w);
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}
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module->connections.push_back(RTLIL::SigSig(data_reg_in[i], sig));
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}
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log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux);
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module->cells.erase(cell->name);
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delete cell;
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return;
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}
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static void handle_module(RTLIL::Module *module)
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{
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std::vector<RTLIL::Cell*> cells;
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for (auto &it : module->cells)
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if (it.second->type == "$mem")
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cells.push_back(it.second);
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for (auto cell : cells)
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handle_cell(module, cell);
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}
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struct MemoryMapPass : public Pass {
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MemoryMapPass() : Pass("memory_map") { }
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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handle_module(mod_it.second);
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}
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} MemoryMapPass;
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