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initial import
This commit is contained in:
Clifford Wolf
commit
7764d0ba1d
481 changed files with 54634 additions and 0 deletions
194
passes/hierarchy/hierarchy.cc
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194
passes/hierarchy/hierarchy.cc
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <set>
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static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check)
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{
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bool did_something = false;
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for (auto &cell_it : module->cells) {
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RTLIL::Cell *cell = cell_it.second;
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if (design->modules.count(cell->type) == 0) {
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if (flag_check && cell->type[0] != '$')
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log_error("Module `%s' referenced in module `%s' in cell `%s' is not part of the design.\n",
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cell->type.c_str(), module->name.c_str(), cell->name.c_str());
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continue;
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}
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if (cell->parameters.size() == 0)
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continue;
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RTLIL::Module *mod = design->modules[cell->type];
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cell->type = mod->derive(design, cell->parameters);
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cell->parameters.clear();
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}
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if (did_something)
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return did_something;
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std::map<RTLIL::SigSpec, int> auto_wires;
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for (auto &wire_it : module->wires) {
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if (wire_it.second->auto_width)
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auto_wires[RTLIL::SigSpec(wire_it.second)] = -1;
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}
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for (auto &cell_it : module->cells)
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for (auto &conn : cell_it.second->connections)
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for (auto &awit : auto_wires) {
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if (awit.second >= 0 || conn.second != awit.first)
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continue;
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if (design->modules.count(cell_it.second->type) == 0) {
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log("WARNING: Module `%s' used in auto-delaration of the wire `%s.%s' cannot be found.\n",
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cell_it.second->type.c_str(), module->name.c_str(), log_signal(awit.first));
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continue;
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}
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RTLIL::Module *mod = design->modules[cell_it.second->type];
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RTLIL::Wire *wire = NULL;
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if (mod->wires.count(conn.first) == 0) {
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for (auto &wire_it : mod->wires) {
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if (wire_it.second->port_id == 0)
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continue;
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char buffer[100];
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snprintf(buffer, 100, "$%d", wire_it.second->port_id);
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if (buffer == conn.first) {
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wire = wire_it.second;
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break;
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}
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}
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} else
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wire = mod->wires[conn.first];
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if (!wire || wire->port_id == 0)
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log_error("No port `%s' found in `%s' but used by instanciation in `%s'!\n",
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conn.first.c_str(), mod->name.c_str(), module->name.c_str());
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if (wire->auto_width)
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log_error("Signal `%s' found in `%s' and used by instanciation in `%s' for an auto wire is an auto-wire itself!\n",
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log_signal(awit.first), mod->name.c_str(), module->name.c_str());
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awit.second = wire->width;
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}
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std::map<RTLIL::IdString, int> auto_sizes;
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for (auto &awit : auto_wires) {
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if (awit.second < 0)
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log("Can't further resolve auto-wire `%s.%s' (width %d) using cell ports.\n",
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module->name.c_str(), awit.first.chunks[0].wire->name.c_str(),
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awit.first.chunks[0].wire->width);
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else
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auto_sizes[awit.first.chunks[0].wire->name] = awit.second;
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}
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if (auto_sizes.size() > 0) {
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module->update_auto_wires(auto_sizes);
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log_header("Continuing EXPAND pass.\n");
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did_something = true;
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}
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return did_something;
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}
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static void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &used, RTLIL::Module *mod, bool is_top = false)
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{
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if (used.count(mod) > 0)
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return;
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log("%s module: %s\n", is_top ? "Top" : "Used", mod->name.c_str());
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used.insert(mod);
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for (auto &it : mod->cells) {
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if (design->modules.count(it.second->type) > 0)
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hierarchy_worker(design, used, design->modules[it.second->type]);
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}
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}
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static void hierarchy(RTLIL::Design *design, RTLIL::Module *top)
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{
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std::set<RTLIL::Module*> used;
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hierarchy_worker(design, used, top, true);
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std::vector<RTLIL::Module*> del_modules;
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for (auto &it : design->modules)
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if (used.count(it.second) == 0)
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del_modules.push_back(it.second);
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for (auto mod : del_modules) {
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log("Removing unused module `%s'.\n", mod->name.c_str());
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design->modules.erase(mod->name);
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delete mod;
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}
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log("Removed %zd unused modules.\n", del_modules.size());
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}
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struct HierarchyPass : public Pass {
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HierarchyPass() : Pass("hierarchy") { }
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing HIERARCHY pass (removing modules outside design hierarchy).\n");
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bool flag_check = false;
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RTLIL::Module *top_mod = NULL;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-check") {
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flag_check = true;
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continue;
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}
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if (args[argidx] == "-top") {
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if (++argidx >= args.size())
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log_cmd_error("Option -top requires an additional argument!\n");
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if (args[argidx][0] != '$' && args[argidx][0] != '\\')
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top_mod = design->modules.count("\\" + args[argidx]) > 0 ? design->modules["\\" + args[argidx]] : NULL;
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else
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top_mod = design->modules.count(args[argidx]) > 0 ? design->modules[args[argidx]] : NULL;
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if (top_mod == NULL)
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log_cmd_error("Module `%s' not found!\n", args[argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (top_mod != NULL)
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hierarchy(design, top_mod);
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bool did_something = true;
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while (did_something) {
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did_something = false;
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std::vector<std::string> modnames;
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modnames.reserve(design->modules.size());
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for (auto &mod_it : design->modules)
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modnames.push_back(mod_it.first);
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for (auto &modname : modnames) {
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if (design->modules.count(modname) == 0)
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continue;
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if (expand_module(design, design->modules[modname], flag_check))
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did_something = true;
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}
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}
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if (top_mod != NULL)
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hierarchy(design, top_mod);
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}
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} HierarchyPass;
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