mirror of
https://github.com/YosysHQ/yosys
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initial import
This commit is contained in:
Clifford Wolf
commit
7764d0ba1d
481 changed files with 54634 additions and 0 deletions
356
passes/fsm/fsm_map.cc
Normal file
356
passes/fsm/fsm_map.cc
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/celltypes.h"
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#include "fsmdata.h"
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#include <string.h>
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static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const, std::set<int>> &pattern_cache, std::set<int> &fullstate_cache, int num_states, RTLIL::Wire *state_onehot, RTLIL::SigSpec &ctrl_in, RTLIL::SigSpec output)
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{
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RTLIL::SigSpec cases_vector;
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for (int in_state : fullstate_cache)
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cases_vector.append(RTLIL::SigSpec(state_onehot, 1, in_state));
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for (auto &it : pattern_cache)
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{
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RTLIL::Const pattern = it.first;
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RTLIL::SigSpec eq_sig_a, eq_sig_b, or_sig;
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for (size_t j = 0; j < pattern.bits.size(); j++)
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if (pattern.bits[j] == RTLIL::State::S0 || pattern.bits[j] == RTLIL::State::S1) {
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eq_sig_a.append(ctrl_in.extract(j, 1));
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eq_sig_b.append(RTLIL::SigSpec(pattern.bits[j]));
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}
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eq_sig_a.optimize();
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eq_sig_b.optimize();
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for (int in_state : it.second)
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if (fullstate_cache.count(in_state) == 0)
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or_sig.append(RTLIL::SigSpec(state_onehot, 1, in_state));
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or_sig.optimize();
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if (or_sig.width == 0)
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continue;
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RTLIL::SigSpec and_sig;
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if (eq_sig_a.width > 0)
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{
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RTLIL::Wire *eq_wire = new RTLIL::Wire;
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eq_wire->name = NEW_ID;
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module->add(eq_wire);
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RTLIL::Cell *eq_cell = new RTLIL::Cell;
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eq_cell->name = NEW_ID;
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eq_cell->type = "$eq";
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eq_cell->connections["\\A"] = eq_sig_a;
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eq_cell->connections["\\B"] = eq_sig_b;
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eq_cell->connections["\\Y"] = RTLIL::SigSpec(eq_wire);
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eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
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eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
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eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.width);
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eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.width);
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eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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module->add(eq_cell);
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and_sig.append(RTLIL::SigSpec(eq_wire));
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}
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if (or_sig.width == 1)
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{
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and_sig.append(or_sig);
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}
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else if (or_sig.width < num_states && int(it.second.size()) < num_states)
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{
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RTLIL::Wire *or_wire = new RTLIL::Wire;
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or_wire->name = NEW_ID;
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module->add(or_wire);
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RTLIL::Cell *or_cell = new RTLIL::Cell;
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or_cell->name = NEW_ID;
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or_cell->type = "$reduce_or";
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or_cell->connections["\\A"] = or_sig;
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or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire);
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or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
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or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.width);
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or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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module->add(or_cell);
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and_sig.append(RTLIL::SigSpec(or_wire));
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}
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switch (and_sig.width)
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{
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case 2:
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{
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RTLIL::Wire *and_wire = new RTLIL::Wire;
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and_wire->name = NEW_ID;
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module->add(and_wire);
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RTLIL::Cell *and_cell = new RTLIL::Cell;
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and_cell->name = NEW_ID;
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and_cell->type = "$and";
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and_cell->connections["\\A"] = and_sig.extract(0, 1);
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and_cell->connections["\\B"] = and_sig.extract(1, 1);
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and_cell->connections["\\Y"] = RTLIL::SigSpec(and_wire);
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and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
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and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
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and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
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and_cell->parameters["\\B_WIDTH"] = RTLIL::Const(1);
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and_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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module->add(and_cell);
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cases_vector.append(RTLIL::SigSpec(and_wire));
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break;
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}
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case 1:
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cases_vector.append(and_sig);
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break;
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case 0:
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cases_vector.append(RTLIL::SigSpec(1, 1));
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break;
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default:
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assert(!"This should never happen!");
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}
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}
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if (cases_vector.width > 1) {
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RTLIL::Cell *or_cell = new RTLIL::Cell;
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or_cell->name = NEW_ID;
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or_cell->type = "$reduce_or";
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or_cell->connections["\\A"] = cases_vector;
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or_cell->connections["\\Y"] = output;
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or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
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or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.width);
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or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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module->add(or_cell);
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} else if (cases_vector.width == 1) {
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module->connections.push_back(RTLIL::SigSig(output, cases_vector));
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} else {
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module->connections.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1)));
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}
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}
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static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
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{
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log("Mapping FSM `%s' from module `%s'.\n", fsm_cell->name.c_str(), module->name.c_str());
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FsmData fsm_data;
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fsm_data.copy_from_cell(fsm_cell);
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RTLIL::SigSpec ctrl_in = fsm_cell->connections["\\CTRL_IN"];
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RTLIL::SigSpec ctrl_out = fsm_cell->connections["\\CTRL_OUT"];
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// create state register
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RTLIL::Wire *state_wire = new RTLIL::Wire;
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state_wire->name = fsm_cell->parameters["\\NAME"].str;
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while (module->count_id(state_wire->name) > 0)
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state_wire->name += "_";
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state_wire->width = fsm_data.state_bits;
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module->add(state_wire);
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RTLIL::Wire *next_state_wire = new RTLIL::Wire;
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next_state_wire->name = NEW_ID;
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next_state_wire->width = fsm_data.state_bits;
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module->add(next_state_wire);
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RTLIL::Cell *state_dff = new RTLIL::Cell;
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state_dff->name = NEW_ID;
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if (fsm_cell->connections["\\ARST"].is_fully_const()) {
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state_dff->type = "$dff";
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} else {
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state_dff->type = "$adff";
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state_dff->parameters["\\ARST_POLARITY"] = fsm_cell->parameters["\\ARST_POLARITY"];
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state_dff->parameters["\\ARST_VALUE"] = fsm_data.state_table[fsm_data.reset_state];
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state_dff->connections["\\ARST"] = fsm_cell->connections["\\ARST"];
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}
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state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits);
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state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"];
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state_dff->connections["\\CLK"] = fsm_cell->connections["\\CLK"];
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state_dff->connections["\\D"] = RTLIL::SigSpec(next_state_wire);
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state_dff->connections["\\Q"] = RTLIL::SigSpec(state_wire);
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module->add(state_dff);
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// decode state register
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bool encoding_is_onehot = true;
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RTLIL::Wire *state_onehot = new RTLIL::Wire;
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state_onehot->name = NEW_ID;
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state_onehot->width = fsm_data.state_table.size();
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module->add(state_onehot);
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for (size_t i = 0; i < fsm_data.state_table.size(); i++)
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{
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RTLIL::Const state = fsm_data.state_table[i];
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RTLIL::SigSpec sig_a, sig_b;
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for (size_t j = 0; j < state.bits.size(); j++)
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if (state.bits[j] == RTLIL::State::S0 || state.bits[j] == RTLIL::State::S1) {
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sig_a.append(RTLIL::SigSpec(state_wire, 1, j));
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sig_b.append(RTLIL::SigSpec(state.bits[j]));
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}
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sig_a.optimize();
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sig_b.optimize();
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if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
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{
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module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, 1, i), sig_a));
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}
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else
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{
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if (sig_b.as_bool() || sig_b.width != fsm_data.state_bits)
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encoding_is_onehot = false;
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RTLIL::Cell *eq_cell = new RTLIL::Cell;
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eq_cell->name = NEW_ID;
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eq_cell->type = "$eq";
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eq_cell->connections["\\A"] = sig_a;
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eq_cell->connections["\\B"] = sig_b;
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eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, 1, i);
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eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
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eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
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eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.width);
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eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.width);
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eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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module->add(eq_cell);
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}
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}
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// generate next_state signal
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RTLIL::Wire *next_state_onehot = new RTLIL::Wire;
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next_state_onehot->name = NEW_ID;
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next_state_onehot->width = fsm_data.state_table.size();
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module->add(next_state_onehot);
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for (size_t i = 0; i < fsm_data.state_table.size(); i++)
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{
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std::map<RTLIL::Const, std::set<int>> pattern_cache;
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std::set<int> fullstate_cache;
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for (size_t j = 0; j < fsm_data.state_table.size(); j++)
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fullstate_cache.insert(j);
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for (auto &tr : fsm_data.transition_table) {
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if (tr.state_out == int(i))
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pattern_cache[tr.ctrl_in].insert(tr.state_in);
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else
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fullstate_cache.erase(tr.state_in);
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}
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implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, 1, i));
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}
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if (encoding_is_onehot)
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{
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for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
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RTLIL::Const state = fsm_data.state_table[i];
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int bit_idx = -1;
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for (size_t j = 0; j < state.bits.size(); j++)
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if (state.bits[j] == RTLIL::State::S1)
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bit_idx = j;
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if (bit_idx >= 0)
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module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(next_state_wire, 1, bit_idx), RTLIL::SigSpec(next_state_onehot, 1, i)));
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}
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}
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else
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{
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RTLIL::SigSpec sig_a, sig_b, sig_s;
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int reset_state = fsm_data.reset_state;
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if (reset_state < 0)
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reset_state = 0;
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for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
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RTLIL::Const state = fsm_data.state_table[i];
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if (int(i) == fsm_data.reset_state) {
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sig_a = RTLIL::SigSpec(state);
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} else {
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sig_b.append(RTLIL::SigSpec(state));
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sig_s.append(RTLIL::SigSpec(next_state_onehot, 1, i));
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}
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}
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RTLIL::Cell *mux_cell = new RTLIL::Cell;
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mux_cell->name = NEW_ID;
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mux_cell->type = "$safe_pmux";
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mux_cell->connections["\\A"] = sig_a;
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mux_cell->connections["\\B"] = sig_b;
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mux_cell->connections["\\S"] = sig_s;
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mux_cell->connections["\\Y"] = RTLIL::SigSpec(next_state_wire);
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mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.width);
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mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.width);
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module->add(mux_cell);
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}
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// Generate ctrl_out signal
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RTLIL::Wire *ctrl_out_wire = new RTLIL::Wire;
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ctrl_out_wire->name = NEW_ID;
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ctrl_out_wire->width = fsm_data.num_outputs;
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module->add(ctrl_out_wire);
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for (int i = 0; i < fsm_data.num_outputs; i++)
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{
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std::map<RTLIL::Const, std::set<int>> pattern_cache;
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std::set<int> fullstate_cache;
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for (size_t j = 0; j < fsm_data.state_table.size(); j++)
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fullstate_cache.insert(j);
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for (auto &tr : fsm_data.transition_table) {
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if (tr.ctrl_out.bits[i] == RTLIL::State::S1)
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pattern_cache[tr.ctrl_in].insert(tr.state_in);
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else
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fullstate_cache.erase(tr.state_in);
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}
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implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, ctrl_out.extract(i, 1));
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}
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// Remove FSM cell
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module->cells.erase(fsm_cell->name);
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delete fsm_cell;
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}
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struct FsmMapPass : public Pass {
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FsmMapPass() : Pass("fsm_map") { }
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing FSM_MAP pass (simple optimizations of FSMs).\n");
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules) {
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std::vector<RTLIL::Cell*> fsm_cells;
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for (auto &cell_it : mod_it.second->cells)
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if (cell_it.second->type == "$fsm")
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fsm_cells.push_back(cell_it.second);
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for (auto cell : fsm_cells)
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map_fsm(cell, mod_it.second);
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}
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}
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} FsmMapPass;
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