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https://github.com/YosysHQ/yosys
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This commit is contained in:
Clifford Wolf
commit
7764d0ba1d
481 changed files with 54634 additions and 0 deletions
415
kernel/sigtools.h
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415
kernel/sigtools.h
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef SIGTOOLS_H
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#define SIGTOOLS_H
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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#include <assert.h>
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#include <set>
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struct SigPool
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{
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typedef std::pair<RTLIL::Wire*,int> bitDef_t;
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std::set<bitDef_t> bits;
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void clear()
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{
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bits.clear();
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}
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void add(RTLIL::SigSpec sig)
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{
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sig.expand();
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for (auto &c : sig.chunks) {
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if (c.wire == NULL)
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continue;
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assert(c.width == 1);
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bitDef_t bit(c.wire, c.offset);
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bits.insert(bit);
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}
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}
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void add(const SigPool &other)
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{
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for (auto &bit : other.bits)
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bits.insert(bit);
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}
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void del(RTLIL::SigSpec sig)
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{
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sig.expand();
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for (auto &c : sig.chunks) {
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if (c.wire == NULL)
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continue;
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assert(c.width == 1);
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bitDef_t bit(c.wire, c.offset);
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bits.erase(bit);
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}
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}
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void del(const SigPool &other)
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{
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for (auto &bit : other.bits)
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bits.insert(bit);
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}
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void expand(RTLIL::SigSpec from, RTLIL::SigSpec to)
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{
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from.expand();
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to.expand();
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assert(from.chunks.size() == to.chunks.size());
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for (size_t i = 0; i < from.chunks.size(); i++) {
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bitDef_t bit_from(from.chunks[i].wire, from.chunks[i].offset);
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bitDef_t bit_to(to.chunks[i].wire, to.chunks[i].offset);
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if (bit_from.first == NULL || bit_to.first == NULL)
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continue;
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if (bits.count(bit_from) > 0)
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bits.insert(bit_to);
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}
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}
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RTLIL::SigSpec extract(RTLIL::SigSpec sig)
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{
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RTLIL::SigSpec result;
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sig.expand();
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for (auto &c : sig.chunks) {
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if (c.wire == NULL)
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continue;
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bitDef_t bit(c.wire, c.offset);
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if (bits.count(bit) > 0)
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result.append(c);
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}
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return result;
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}
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RTLIL::SigSpec remove(RTLIL::SigSpec sig)
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{
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RTLIL::SigSpec result;
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sig.expand();
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for (auto &c : sig.chunks) {
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if (c.wire == NULL)
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continue;
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bitDef_t bit(c.wire, c.offset);
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if (bits.count(bit) == 0)
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result.append(c);
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}
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return result;
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}
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bool check_any(RTLIL::SigSpec sig)
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{
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sig.expand();
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for (auto &c : sig.chunks) {
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if (c.wire == NULL)
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continue;
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bitDef_t bit(c.wire, c.offset);
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if (bits.count(bit) != 0)
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return true;
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}
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return false;
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}
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bool check_all(RTLIL::SigSpec sig)
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{
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sig.expand();
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for (auto &c : sig.chunks) {
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if (c.wire == NULL)
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continue;
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bitDef_t bit(c.wire, c.offset);
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if (bits.count(bit) == 0)
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return false;
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}
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return true;
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}
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};
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template <typename T>
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struct SigSet
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{
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typedef std::pair<RTLIL::Wire*,int> bitDef_t;
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std::map<bitDef_t, std::set<T>> bits;
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void clear()
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{
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bits.clear();
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}
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void insert(RTLIL::SigSpec sig, T data)
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{
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sig.expand();
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for (auto &c : sig.chunks) {
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if (c.wire == NULL)
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continue;
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assert(c.width == 1);
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bitDef_t bit(c.wire, c.offset);
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bits[bit].insert(data);
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}
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}
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void erase(RTLIL::SigSpec sig)
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{
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sig.expand();
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for (auto &c : sig.chunks) {
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if (c.wire == NULL)
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continue;
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assert(c.width == 1);
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bitDef_t bit(c.wire, c.offset);
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bits[bit].clear();
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}
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}
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void erase(RTLIL::SigSpec sig, T data)
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{
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sig.expand();
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for (auto &c : sig.chunks) {
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if (c.wire == NULL)
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continue;
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assert(c.width == 1);
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bitDef_t bit(c.wire, c.offset);
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bits[bit].erase(data);
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}
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}
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void find(RTLIL::SigSpec sig, std::set<T> &result)
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{
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sig.expand();
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for (auto &c : sig.chunks) {
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if (c.wire == NULL)
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continue;
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assert(c.width == 1);
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bitDef_t bit(c.wire, c.offset);
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for (auto &data : bits[bit])
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result.insert(data);
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}
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}
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std::set<T> find(RTLIL::SigSpec sig)
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{
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std::set<T> result;
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find(sig, result);
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return result;
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}
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};
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struct SigMap
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{
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typedef std::pair<RTLIL::Wire*,int> bitDef_t;
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struct shared_bit_data_t {
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RTLIL::SigChunk chunk;
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std::set<bitDef_t> bits;
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};
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std::map<bitDef_t, shared_bit_data_t*> bits;
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SigMap(RTLIL::Module *module = NULL)
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{
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if (module != NULL)
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set(module);
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}
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SigMap(const SigMap &other)
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{
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copy(other);
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}
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const SigMap &operator=(const SigMap &other)
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{
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copy(other);
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return *this;
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}
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void copy(const SigMap &other)
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{
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clear();
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for (auto &bit : other.bits) {
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bits[bit.first] = new shared_bit_data_t;
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bits[bit.first]->chunk = bit.second->chunk;
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bits[bit.first]->bits = bit.second->bits;
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}
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}
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void swap(SigMap &other)
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{
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bits.swap(other.bits);
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}
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~SigMap()
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{
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clear();
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}
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void clear()
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{
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std::set<shared_bit_data_t*> all_bd_ptr;
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for (auto &it : bits)
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all_bd_ptr.insert(it.second);
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for (auto bd_ptr : all_bd_ptr)
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delete bd_ptr;
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bits.clear();
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}
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void set(RTLIL::Module *module)
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{
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clear();
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for (auto &it : module->connections)
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add(it.first, it.second);
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}
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// internal helper function
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void register_bit(const RTLIL::SigChunk &c)
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{
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assert(c.width == 1);
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bitDef_t bit(c.wire, c.offset);
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if (c.wire && bits.count(bit) == 0) {
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shared_bit_data_t *bd = new shared_bit_data_t;
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bd->chunk = c;
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bd->bits.insert(bit);
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bits[bit] = bd;
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}
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}
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// internal helper function
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void unregister_bit(const RTLIL::SigChunk &c)
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{
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assert(c.width == 1);
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bitDef_t bit(c.wire, c.offset);
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if (c.wire && bits.count(bit) > 0) {
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shared_bit_data_t *bd = bits[bit];
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bd->bits.erase(bit);
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if (bd->bits.size() == 0)
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delete bd;
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bits.erase(bit);
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}
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}
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// internal helper function
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void merge_bit(const RTLIL::SigChunk &c1, const RTLIL::SigChunk &c2)
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{
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assert(c1.wire != NULL && c2.wire != NULL);
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assert(c1.width == 1 && c2.width == 1);
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bitDef_t b1(c1.wire, c1.offset);
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bitDef_t b2(c2.wire, c2.offset);
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shared_bit_data_t *bd1 = bits[b1];
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shared_bit_data_t *bd2 = bits[b2];
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assert(bd1 != NULL && bd2 != NULL);
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if (bd1 == bd2)
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return;
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if (bd1->bits.size() < bd2->bits.size())
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{
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for (auto &bit : bd1->bits)
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bits[bit] = bd2;
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bd2->bits.insert(bd1->bits.begin(), bd1->bits.end());
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delete bd1;
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}
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else
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{
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bd1->chunk = bd2->chunk;
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for (auto &bit : bd2->bits)
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bits[bit] = bd1;
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bd1->bits.insert(bd2->bits.begin(), bd2->bits.end());
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delete bd2;
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}
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}
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// internal helper function
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void set_bit(const RTLIL::SigChunk &c1, const RTLIL::SigChunk &c2)
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{
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assert(c1.wire != NULL);
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assert(c1.width == 1 && c2.width == 1);
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bitDef_t bit(c1.wire, c1.offset);
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assert(bits.count(bit) > 0);
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bits[bit]->chunk = c2;
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}
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// internal helper function
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void map_bit(RTLIL::SigChunk &c)
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{
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assert(c.width == 1);
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bitDef_t bit(c.wire, c.offset);
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if (c.wire && bits.count(bit) > 0)
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c = bits[bit]->chunk;
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}
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void add(RTLIL::SigSpec from, RTLIL::SigSpec to)
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{
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from.expand();
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to.expand();
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assert(from.chunks.size() == to.chunks.size());
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for (size_t i = 0; i < from.chunks.size(); i++)
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{
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RTLIL::SigChunk &cf = from.chunks[i];
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RTLIL::SigChunk &ct = to.chunks[i];
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if (cf.wire == NULL)
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continue;
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register_bit(cf);
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register_bit(ct);
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if (ct.wire != NULL)
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merge_bit(cf, ct);
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else
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set_bit(cf, ct);
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}
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}
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void add(RTLIL::SigSpec sig)
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{
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sig.expand();
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for (size_t i = 0; i < sig.chunks.size(); i++)
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{
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RTLIL::SigChunk &c = sig.chunks[i];
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if (c.wire != NULL) {
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register_bit(c);
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set_bit(c, c);
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}
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}
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}
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void del(RTLIL::SigSpec sig)
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{
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sig.expand();
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for (auto &c : sig.chunks)
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unregister_bit(c);
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}
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void apply(RTLIL::SigSpec &sig)
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{
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sig.expand();
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for (auto &c : sig.chunks)
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map_bit(c);
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sig.optimize();
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}
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RTLIL::SigSpec operator()(RTLIL::SigSpec sig)
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{
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apply(sig);
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return sig;
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}
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};
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#endif /* SIGTOOLS_H */
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