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https://github.com/YosysHQ/yosys
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initial import
This commit is contained in:
Clifford Wolf
commit
7764d0ba1d
481 changed files with 54634 additions and 0 deletions
341
kernel/rtlil.h
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341
kernel/rtlil.h
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef RTLIL_H
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#define RTLIL_H
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#include <map>
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#include <set>
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#include <vector>
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#include <string>
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#include <assert.h>
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std::string stringf(const char *fmt, ...);
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namespace RTLIL
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{
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enum State {
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S0 = 0,
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S1 = 1,
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Sx = 2, // undefined value or conflict
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Sz = 3, // high-impedance / not-connected
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Sa = 4, // don't care (used only in cases)
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Sm = 5 // marker (used internally by some passes)
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};
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enum SyncType {
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ST0 = 0, // level sensitive: 0
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ST1 = 1, // level sensitive: 1
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STp = 2, // edge sensitive: posedge
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STn = 3, // edge sensitive: negedge
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STe = 4, // edge sensitive: both edges
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STa = 5 // always active
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};
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extern int autoidx;
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struct Const;
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struct Selection;
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struct Design;
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struct Module;
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struct Wire;
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struct Memory;
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struct Cell;
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struct SigChunk;
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struct SigSpec;
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struct CaseRule;
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struct SwitchRule;
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struct SyncRule;
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struct Process;
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typedef std::pair<SigSpec, SigSpec> SigSig;
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#ifdef NDEBUG
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typedef std::string IdString;
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#else
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struct IdString : public std::string {
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IdString() { }
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IdString(std::string str) : std::string(str) {
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check();
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}
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IdString(const char *s) : std::string(s) {
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check();
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}
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IdString &operator=(const std::string &str) {
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std::string::operator=(str);
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check();
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return *this;
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}
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IdString &operator=(const char *s) {
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std::string::operator=(s);
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check();
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return *this;
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}
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bool operator<(const IdString &rhs) {
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check(), rhs.check();
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return std::string(*this) < std::string(rhs);
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}
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void check() const {
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assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\')));
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}
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};
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#endif
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static IdString escape_id(std::string str) __attribute__((unused));
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static IdString escape_id(std::string str) {
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if (str.size() > 0 && str[0] != '\\' && str[0] != '$')
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return "\\" + str;
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return str;
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}
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static std::string unescape_id(std::string str) __attribute__((unused));
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static std::string unescape_id(std::string str) {
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if (str.size() > 0 && str[0] == '\\')
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return str.substr(1);
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return str;
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}
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static IdString new_id(std::string file, int line, std::string func) __attribute__((unused));
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static IdString new_id(std::string file, int line, std::string func) {
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std::string str = "$auto$";
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size_t pos = file.find_last_of('/');
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str += pos != std::string::npos ? file.substr(pos+1) : file;
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str += stringf(":%d:%s$%d", line, func.c_str(), autoidx++);
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return str;
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}
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#define NEW_ID \
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RTLIL::new_id(__FILE__, __LINE__, __FUNCTION__)
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// see calc.cc for the implementation of this functions
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RTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_reduce_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_reduce_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_reduce_xor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_reduce_xnor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_reduce_bool (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_logic_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_logic_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_logic_or (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_shl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_shr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_sshl (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_sshr (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_lt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_le (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_eq (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_ne (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_ge (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_gt (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_add (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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RTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
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};
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struct RTLIL::Const {
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std::string str;
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std::vector<RTLIL::State> bits;
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Const(std::string str = std::string());
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Const(int val, int width = 32);
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Const(RTLIL::State bit, int width = 1);
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Const(std::vector<RTLIL::State> bits) : bits(bits) { };
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bool operator <(const RTLIL::Const &other) const;
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bool operator ==(const RTLIL::Const &other) const;
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bool operator !=(const RTLIL::Const &other) const;
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bool as_bool() const;
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int as_int() const;
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std::string as_string() const;
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};
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struct RTLIL::Selection {
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bool full_selection;
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std::set<RTLIL::IdString> selected_modules;
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std::map<RTLIL::IdString, std::set<RTLIL::IdString>> selected_members;
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Selection(bool full = true) : full_selection(full) { }
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bool selected_module(RTLIL::IdString mod_name);
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bool selected_whole_module(RTLIL::IdString mod_name);
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bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name);
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void optimize(RTLIL::Design *design);
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};
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struct RTLIL::Design {
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std::map<RTLIL::IdString, RTLIL::Module*> modules;
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std::vector<RTLIL::Selection> selection_stack;
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std::map<RTLIL::IdString, RTLIL::Selection> selection_vars;
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std::string selected_active_module;
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~Design();
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void check();
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void optimize();
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bool selected_module(RTLIL::IdString mod_name);
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bool selected_whole_module(RTLIL::IdString mod_name);
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bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name);
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template<typename T1> bool selected(T1 *module) {
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return selected_module(module->name);
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}
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template<typename T1, typename T2> bool selected(T1 *module, T2 *member) {
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return selected_member(module->name, member->name);
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}
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};
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struct RTLIL::Module {
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RTLIL::IdString name;
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std::map<RTLIL::IdString, RTLIL::Wire*> wires;
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std::map<RTLIL::IdString, RTLIL::Memory*> memories;
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std::map<RTLIL::IdString, RTLIL::Cell*> cells;
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std::map<RTLIL::IdString, RTLIL::Process*> processes;
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std::vector<RTLIL::SigSig> connections;
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std::map<RTLIL::IdString, RTLIL::Const> attributes;
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virtual ~Module();
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virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
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virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes);
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virtual size_t count_id(RTLIL::IdString id);
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virtual void check();
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virtual void optimize();
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void add(RTLIL::Wire *wire);
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void add(RTLIL::Cell *cell);
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};
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struct RTLIL::Wire {
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RTLIL::IdString name;
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int width, start_offset, port_id;
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bool port_input, port_output, auto_width;
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std::map<RTLIL::IdString, RTLIL::Const> attributes;
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Wire();
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};
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struct RTLIL::Memory {
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RTLIL::IdString name;
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int width, start_offset, size;
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std::map<RTLIL::IdString, RTLIL::Const> attributes;
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Memory();
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};
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struct RTLIL::Cell {
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RTLIL::IdString name;
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RTLIL::IdString type;
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std::map<RTLIL::IdString, RTLIL::SigSpec> connections;
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std::map<RTLIL::IdString, RTLIL::Const> attributes;
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std::map<RTLIL::IdString, RTLIL::Const> parameters;
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void optimize();
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};
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struct RTLIL::SigChunk {
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RTLIL::Wire *wire;
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RTLIL::Const data; // only used if wire == NULL, LSB at index 0
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int width, offset;
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SigChunk();
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SigChunk(const RTLIL::Const &data);
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SigChunk(RTLIL::Wire *wire, int width, int offset);
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SigChunk(const std::string &str);
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SigChunk(int val, int width = 32);
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SigChunk(RTLIL::State bit, int width = 1);
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RTLIL::SigChunk extract(int offset, int length) const;
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bool operator <(const RTLIL::SigChunk &other) const;
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bool operator ==(const RTLIL::SigChunk &other) const;
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bool operator !=(const RTLIL::SigChunk &other) const;
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};
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struct RTLIL::SigSpec {
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std::vector<RTLIL::SigChunk> chunks; // LSB at index 0
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int width;
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SigSpec();
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SigSpec(const RTLIL::Const &data);
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SigSpec(const RTLIL::SigChunk &chunk);
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SigSpec(RTLIL::Wire *wire, int width = -1, int offset = 0);
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SigSpec(const std::string &str);
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SigSpec(int val, int width = 32);
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SigSpec(RTLIL::State bit, int width = 1);
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void expand();
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void optimize();
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void sort_and_unify();
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void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with);
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void replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with, RTLIL::SigSpec *other) const;
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void remove(const RTLIL::SigSpec &pattern);
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void remove(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other) const;
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void remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *other);
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RTLIL::SigSpec extract(RTLIL::SigSpec pattern, RTLIL::SigSpec *other = NULL) const;
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void replace(int offset, const RTLIL::SigSpec &with);
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void remove_const();
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void remove(int offset, int length);
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RTLIL::SigSpec extract(int offset, int length) const;
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void append(const RTLIL::SigSpec &signal);
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bool combine(RTLIL::SigSpec signal, RTLIL::State freeState = RTLIL::State::Sz, bool override = false);
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void extend(int width, bool is_signed = false);
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void check() const;
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bool operator <(const RTLIL::SigSpec &other) const;
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bool operator ==(const RTLIL::SigSpec &other) const;
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bool operator !=(const RTLIL::SigSpec &other) const;
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bool is_fully_const() const;
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bool is_fully_def() const;
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bool is_fully_undef() const;
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bool has_marked_bits() const;
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bool as_bool() const;
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int as_int() const;
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std::string as_string() const;
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RTLIL::Const as_const() const;
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bool match(std::string pattern) const;
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};
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struct RTLIL::CaseRule {
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std::vector<RTLIL::SigSpec> compare;
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std::vector<RTLIL::SigSig> actions;
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std::vector<RTLIL::SwitchRule*> switches;
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~CaseRule();
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void optimize();
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};
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struct RTLIL::SwitchRule {
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RTLIL::SigSpec signal;
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std::map<RTLIL::IdString, RTLIL::Const> attributes;
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std::vector<RTLIL::CaseRule*> cases;
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~SwitchRule();
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void optimize();
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};
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struct RTLIL::SyncRule {
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RTLIL::SyncType type;
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RTLIL::SigSpec signal;
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std::vector<RTLIL::SigSig> actions;
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void optimize();
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};
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struct RTLIL::Process {
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RTLIL::IdString name;
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std::map<RTLIL::IdString, RTLIL::Const> attributes;
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RTLIL::CaseRule root_case;
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std::vector<RTLIL::SyncRule*> syncs;
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~Process();
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void optimize();
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};
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#endif
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