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https://github.com/YosysHQ/yosys
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initial import
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Clifford Wolf
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264
frontends/verilog/lexer.l
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264
frontends/verilog/lexer.l
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The Verilog frontend.
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*
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* This frontend is using the AST frontend library (see frontends/ast/).
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* Thus this frontend does not generate RTLIL code directly but creates an
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* AST directly from the Verilog parse tree and then passes this AST to
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* the AST frontend library.
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*
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* ---
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*
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* A simple lexer for Verilog code. Non-preprocessor compiler directives are
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* handled here. The preprocessor stuff is handled in preproc.cc. Everything
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* else is left to the bison parser (see parser.y).
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*
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*/
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%{
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#include "kernel/log.h"
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#include "verilog_frontend.h"
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#include "frontends/ast/ast.h"
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#include "parser.tab.h"
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using namespace AST;
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using namespace VERILOG_FRONTEND;
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namespace VERILOG_FRONTEND {
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std::vector<std::string> fn_stack;
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std::vector<int> ln_stack;
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bool lexer_feature_defattr;
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}
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%}
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%option yylineno
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%option noyywrap
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%option nounput
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%option prefix="frontend_verilog_yy"
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%x COMMENT
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%x STRING
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%x SYNOPSYS_TRANSLATE_OFF
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%x SYNOPSYS_FLAGS
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%%
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"`file_push "[^\n]* {
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fn_stack.push_back(current_filename);
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ln_stack.push_back(frontend_verilog_yyget_lineno());
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current_filename = yytext+11;
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frontend_verilog_yyset_lineno(0);
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}
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"`file_pop"[^\n]*\n {
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current_filename = fn_stack.back();
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frontend_verilog_yyset_lineno(ln_stack.back());
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}
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"`file_notfound "[^\n]* {
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log_error("Can't open include file `%s'!\n", yytext + 15);
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}
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"`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
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"`yosys_enable_defattr" lexer_feature_defattr = true;
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"`yosys_disable_defattr" lexer_feature_defattr = false;
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"`"[a-zA-Z_$][a-zA-Z0-9_$]* {
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frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
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}
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"module" { return TOK_MODULE; }
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"endmodule" { return TOK_ENDMODULE; }
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"function" { return TOK_FUNCTION; }
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"endfunction" { return TOK_ENDFUNCTION; }
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"task" { return TOK_TASK; }
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"endtask" { return TOK_ENDTASK; }
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"parameter" { return TOK_PARAMETER; }
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"localparam" { return TOK_LOCALPARAM; }
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"assign" { return TOK_ASSIGN; }
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"always" { return TOK_ALWAYS; }
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"initial" { return TOK_INITIAL; }
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"begin" { return TOK_BEGIN; }
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"end" { return TOK_END; }
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"if" { return TOK_IF; }
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"else" { return TOK_ELSE; }
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"for" { return TOK_FOR; }
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"posedge" { return TOK_POSEDGE; }
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"negedge" { return TOK_NEGEDGE; }
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"or" { return TOK_OR; }
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"case" { return TOK_CASE; }
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"casex" { return TOK_CASEX; }
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"casez" { return TOK_CASEZ; }
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"endcase" { return TOK_ENDCASE; }
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"default" { return TOK_DEFAULT; }
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"generate" { return TOK_GENERATE; }
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"endgenerate" { return TOK_ENDGENERATE; }
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"input" { return TOK_INPUT; }
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"output" { return TOK_OUTPUT; }
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"inout" { return TOK_INOUT; }
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"wire" { return TOK_WIRE; }
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"reg" { return TOK_REG; }
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"integer" { return TOK_INTEGER; }
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"signed" { return TOK_SIGNED; }
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"genvar" { return TOK_GENVAR; }
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[0-9]+ {
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frontend_verilog_yylval.string = new std::string(yytext);
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return TOK_CONST;
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}
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[0-9]*[ \t]*\'s?[bodh][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
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frontend_verilog_yylval.string = new std::string(yytext);
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return TOK_CONST;
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}
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\" { BEGIN(STRING); }
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<STRING>\\. { yymore(); }
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<STRING>\" {
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BEGIN(0);
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char *yystr = strdup(yytext);
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yystr[strlen(yytext) - 1] = 0;
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int i = 0, j = 0;
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while (yystr[i]) {
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if (yystr[i] == '\\' && yystr[i + 1]) {
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i++;
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if (yystr[i] == 'n')
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yystr[i] = '\n';
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else if (yystr[i] == 't')
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yystr[i] = '\t';
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else if ('0' <= yystr[i] && yystr[i] <= '7') {
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yystr[i] = yystr[i] - '0';
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if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
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yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
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i++;
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}
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if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
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yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
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i++;
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}
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}
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}
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yystr[j++] = yystr[i++];
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}
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yystr[j] = 0;
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frontend_verilog_yylval.string = new std::string(yystr);
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free(yystr);
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return TOK_STRING;
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}
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<STRING>. { yymore(); }
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and|nand|or|nor|xor|xnor|not|buf {
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frontend_verilog_yylval.string = new std::string(yytext);
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return TOK_PRIMITIVE;
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}
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supply0 { return TOK_SUPPLY0; }
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supply1 { return TOK_SUPPLY1; }
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"$"(display|time|stop|finish) {
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frontend_verilog_yylval.string = new std::string(yytext);
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return TOK_ID;
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}
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"$signed" { return TOK_TO_SIGNED; }
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"$unsigned" { return TOK_TO_UNSIGNED; }
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[a-zA-Z_$][a-zA-Z0-9_$]* {
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frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
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return TOK_ID;
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}
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"/*"[ \t]*synopsys[ \t]*translate_off[ \t]*"*/" {
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log("Warning: Found one of those horrible `synopsys translate_off' comments.\n");
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log("It is strongly suggested to use `ifdef constructs instead!\n");
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BEGIN(SYNOPSYS_TRANSLATE_OFF);
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}
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<SYNOPSYS_TRANSLATE_OFF>. /* ignore synopsys translate_off body */
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<SYNOPSYS_TRANSLATE_OFF>\n /* ignore synopsys translate_off body */
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<SYNOPSYS_TRANSLATE_OFF>"/*"[ \t]*"synopsys"[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); }
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"/*"[ \t]*"synopsys"[ \t]+ {
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BEGIN(SYNOPSYS_FLAGS);
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}
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<SYNOPSYS_FLAGS>full_case {
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log("Warning: Found one of those horrible `synopsys full_case' comments.\n");
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log("It is strongly suggested to use verilog x-values and default branches instead!\n");
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return TOK_SYNOPSYS_FULL_CASE;
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}
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<SYNOPSYS_FLAGS>parallel_case {
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log("Warning: Found one of those horrible `synopsys parallel_case' comments.\n");
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log("It is strongly suggested to use verilog `parallel_case' attributes instead!\n");
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return TOK_SYNOPSYS_PARALLEL_CASE;
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}
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<SYNOPSYS_FLAGS>. /* ignore everything else */
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<SYNOPSYS_FLAGS>"*/" { BEGIN(0); }
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"\\"[^ \t\r\n]+ {
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frontend_verilog_yylval.string = new std::string(yytext);
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return TOK_ID;
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}
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"(*" { return ATTR_BEGIN; }
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"*)" { return ATTR_END; }
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"{*" { if (lexer_feature_defattr) return DEFATTR_BEGIN; else REJECT; }
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"*}" { if (lexer_feature_defattr) return DEFATTR_END; else REJECT; }
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"**" { return OP_POW; }
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"||" { return OP_LOR; }
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"&&" { return OP_LAND; }
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"==" { return OP_EQ; }
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"!=" { return OP_NE; }
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"<=" { return OP_LE; }
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">=" { return OP_GE; }
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/* "~&" { return OP_NAND; } */
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/* "~|" { return OP_NOR; } */
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"~^" { return OP_XNOR; }
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"^~" { return OP_XNOR; }
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"<<" { return OP_SHL; }
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">>" { return OP_SHR; }
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"<<<" { return OP_SSHL; }
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">>>" { return OP_SSHR; }
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"/*" { BEGIN(COMMENT); }
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<COMMENT>. /* ignore comment body */
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<COMMENT>\n /* ignore comment body */
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<COMMENT>"*/" { BEGIN(0); }
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[ \t\r\n] /* ignore whitespaces */
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\\[\r\n] /* ignore continuation sequence */
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"//"[^\r\n]* /* ignore one-line comments */
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"#"[$a-zA-Z_0-9\.]+ /* ignore simulation timings */
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. { return *yytext; }
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%%
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// this is a hack to avoid the 'yyinput defined but not used' error msgs
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void *frontend_verilog_avoid_input_warnings() {
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return (void*)&yyinput;
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}
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