mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 14:13:23 +00:00
initial import
This commit is contained in:
Clifford Wolf
commit
7764d0ba1d
481 changed files with 54634 additions and 0 deletions
19
frontends/verilog/Makefile.inc
Normal file
19
frontends/verilog/Makefile.inc
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
|
||||
GENFILES += frontends/verilog/parser.tab.cc
|
||||
GENFILES += frontends/verilog/parser.tab.h
|
||||
GENFILES += frontends/verilog/parser.output
|
||||
GENFILES += frontends/verilog/lexer.cc
|
||||
|
||||
frontends/verilog/parser.tab.cc frontends/verilog/parser.tab.h: frontends/verilog/parser.y
|
||||
bison -d -r all -b frontends/verilog/parser frontends/verilog/parser.y
|
||||
mv frontends/verilog/parser.tab.c frontends/verilog/parser.tab.cc
|
||||
|
||||
frontends/verilog/lexer.cc: frontends/verilog/lexer.l
|
||||
flex -o frontends/verilog/lexer.cc frontends/verilog/lexer.l
|
||||
|
||||
OBJS += frontends/verilog/parser.tab.o
|
||||
OBJS += frontends/verilog/lexer.o
|
||||
OBJS += frontends/verilog/preproc.o
|
||||
OBJS += frontends/verilog/verilog_frontend.o
|
||||
OBJS += frontends/verilog/const2ast.o
|
||||
|
||||
197
frontends/verilog/const2ast.cc
Normal file
197
frontends/verilog/const2ast.cc
Normal file
|
|
@ -0,0 +1,197 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* ---
|
||||
*
|
||||
* The Verilog frontend.
|
||||
*
|
||||
* This frontend is using the AST frontend library (see frontends/ast/).
|
||||
* Thus this frontend does not generate RTLIL code directly but creates an
|
||||
* AST directly from the Verilog parse tree and then passes this AST to
|
||||
* the AST frontend library.
|
||||
*
|
||||
* ---
|
||||
*
|
||||
* This file contains an ad-hoc parser for Verilog constants. The Verilog
|
||||
* lexer does only recognize a constant but does not actually split it to its
|
||||
* components. I.e. it just passes the Verilog code for the constant to the
|
||||
* bison parser. The parser then uses the function const2ast() from this file
|
||||
* to create an AST node for the constant.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "verilog_frontend.h"
|
||||
#include "kernel/log.h"
|
||||
#include <assert.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
using namespace AST;
|
||||
|
||||
// divide an arbitrary length decimal number by two and return the rest
|
||||
static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
|
||||
{
|
||||
int carry = 0;
|
||||
for (size_t i = 0; i < digits.size(); i++) {
|
||||
assert(digits[i] < 10);
|
||||
digits[i] += carry * 10;
|
||||
carry = digits[i] % 2;
|
||||
digits[i] /= 2;
|
||||
}
|
||||
return carry;
|
||||
}
|
||||
|
||||
// find the number of significant bits in a binary number (not including the sign bit)
|
||||
static int my_ilog2(int x)
|
||||
{
|
||||
int ret = 0;
|
||||
while (x != 0 && x != -1) {
|
||||
x = x >> 1;
|
||||
ret++;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
// parse a binary, decimal, hexadecimal or octal number with support for special bits ('x', 'z' and '?')
|
||||
static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type)
|
||||
{
|
||||
// all digits in string (MSB at index 0)
|
||||
std::vector<uint8_t> digits;
|
||||
|
||||
while (*str) {
|
||||
if ('0' <= *str && *str <= '9')
|
||||
digits.push_back(*str - '0');
|
||||
else if ('a' <= *str && *str <= 'f')
|
||||
digits.push_back(10 + *str - 'a');
|
||||
else if ('A' <= *str && *str <= 'F')
|
||||
digits.push_back(10 + *str - 'A');
|
||||
else if (*str == 'x' || *str == 'X')
|
||||
digits.push_back(0xf0);
|
||||
else if (*str == 'z' || *str == 'Z')
|
||||
digits.push_back(0xf1);
|
||||
else if (*str == '?')
|
||||
digits.push_back(0xf2);
|
||||
str++;
|
||||
}
|
||||
|
||||
if (base == 10) {
|
||||
data.clear();
|
||||
if (len_in_bits < 0)
|
||||
len_in_bits = ceil(digits.size()/log10(2));
|
||||
for (int i = 0; i < len_in_bits; i++)
|
||||
data.push_back(my_decimal_div_by_two(digits) ? RTLIL::S1 : RTLIL::S0);
|
||||
return;
|
||||
}
|
||||
|
||||
int bits_per_digit = my_ilog2(base-1);
|
||||
if (len_in_bits < 0)
|
||||
len_in_bits = digits.size() * bits_per_digit;
|
||||
|
||||
data.clear();
|
||||
data.resize(len_in_bits);
|
||||
|
||||
for (int i = 0; i < len_in_bits; i++) {
|
||||
int bitmask = 1 << (i % bits_per_digit);
|
||||
int digitidx = digits.size() - (i / bits_per_digit) - 1;
|
||||
if (digitidx < 0) {
|
||||
if (i > 0 && (data[i-1] == RTLIL::Sz || data[i-1] == RTLIL::Sx || data[i-1] == RTLIL::Sa))
|
||||
data[i] = data[i-1];
|
||||
else
|
||||
data[i] = RTLIL::S0;
|
||||
} else if (digits[digitidx] == 0xf0)
|
||||
data[i] = case_type == 'x' ? RTLIL::Sa : RTLIL::Sx;
|
||||
else if (digits[digitidx] == 0xf1)
|
||||
data[i] = case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz;
|
||||
else if (digits[digitidx] == 0xf2)
|
||||
data[i] = RTLIL::Sa;
|
||||
else
|
||||
data[i] = (digits[digitidx] & bitmask) ? RTLIL::S1 : RTLIL::S0;
|
||||
}
|
||||
}
|
||||
|
||||
// convert the verilog code for a constant to an AST node
|
||||
AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
|
||||
{
|
||||
const char *str = code.c_str();
|
||||
|
||||
// Strings
|
||||
if (*str == '"') {
|
||||
int len = strlen(str) - 2;
|
||||
std::vector<RTLIL::State> data;
|
||||
data.reserve(len * 8);
|
||||
for (int i = 0; i < len; i++) {
|
||||
unsigned char ch = str[len - i];
|
||||
for (int j = 0; j < 8; j++) {
|
||||
data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0);
|
||||
ch = ch >> 1;
|
||||
}
|
||||
}
|
||||
AstNode *ast = AstNode::mkconst_bits(data, false);
|
||||
ast->str = code;
|
||||
return ast;
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < code.size(); i++)
|
||||
if (code[i] == '_' || code[i] == ' ' || code[i] == '\t' || code[i] == '\r' || code[i] == '\n')
|
||||
code.erase(code.begin()+(i--));
|
||||
str = code.c_str();
|
||||
|
||||
char *endptr;
|
||||
long intval = strtol(str, &endptr, 10);
|
||||
|
||||
// Simple 32 bit integer
|
||||
if (*endptr == 0)
|
||||
return AstNode::mkconst_int(intval, true);
|
||||
|
||||
// variable length constant
|
||||
if (str == endptr)
|
||||
intval = -1;
|
||||
|
||||
// The "<bits>'[bodh]<digits>" syntax
|
||||
if (*endptr == '\'')
|
||||
{
|
||||
int len_in_bits = intval;
|
||||
std::vector<RTLIL::State> data;
|
||||
bool is_signed = false;
|
||||
if (*(endptr+1) == 's') {
|
||||
is_signed = true;
|
||||
endptr++;
|
||||
}
|
||||
switch (*(endptr+1))
|
||||
{
|
||||
case 'b':
|
||||
my_strtobin(data, endptr+2, len_in_bits, 2, case_type);
|
||||
break;
|
||||
case 'o':
|
||||
my_strtobin(data, endptr+2, len_in_bits, 8, case_type);
|
||||
break;
|
||||
case 'd':
|
||||
my_strtobin(data, endptr+2, len_in_bits, 10, case_type);
|
||||
break;
|
||||
case 'h':
|
||||
my_strtobin(data, endptr+2, len_in_bits, 16, case_type);
|
||||
break;
|
||||
default:
|
||||
goto error;
|
||||
}
|
||||
return AstNode::mkconst_bits(data, is_signed);
|
||||
}
|
||||
|
||||
error:
|
||||
log_error("Value conversion failed: `%s'\n", code.c_str());
|
||||
}
|
||||
|
||||
264
frontends/verilog/lexer.l
Normal file
264
frontends/verilog/lexer.l
Normal file
|
|
@ -0,0 +1,264 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* ---
|
||||
*
|
||||
* The Verilog frontend.
|
||||
*
|
||||
* This frontend is using the AST frontend library (see frontends/ast/).
|
||||
* Thus this frontend does not generate RTLIL code directly but creates an
|
||||
* AST directly from the Verilog parse tree and then passes this AST to
|
||||
* the AST frontend library.
|
||||
*
|
||||
* ---
|
||||
*
|
||||
* A simple lexer for Verilog code. Non-preprocessor compiler directives are
|
||||
* handled here. The preprocessor stuff is handled in preproc.cc. Everything
|
||||
* else is left to the bison parser (see parser.y).
|
||||
*
|
||||
*/
|
||||
|
||||
%{
|
||||
|
||||
#include "kernel/log.h"
|
||||
#include "verilog_frontend.h"
|
||||
#include "frontends/ast/ast.h"
|
||||
#include "parser.tab.h"
|
||||
|
||||
using namespace AST;
|
||||
using namespace VERILOG_FRONTEND;
|
||||
|
||||
namespace VERILOG_FRONTEND {
|
||||
std::vector<std::string> fn_stack;
|
||||
std::vector<int> ln_stack;
|
||||
bool lexer_feature_defattr;
|
||||
}
|
||||
|
||||
%}
|
||||
|
||||
%option yylineno
|
||||
%option noyywrap
|
||||
%option nounput
|
||||
%option prefix="frontend_verilog_yy"
|
||||
|
||||
%x COMMENT
|
||||
%x STRING
|
||||
%x SYNOPSYS_TRANSLATE_OFF
|
||||
%x SYNOPSYS_FLAGS
|
||||
|
||||
%%
|
||||
|
||||
"`file_push "[^\n]* {
|
||||
fn_stack.push_back(current_filename);
|
||||
ln_stack.push_back(frontend_verilog_yyget_lineno());
|
||||
current_filename = yytext+11;
|
||||
frontend_verilog_yyset_lineno(0);
|
||||
}
|
||||
|
||||
"`file_pop"[^\n]*\n {
|
||||
current_filename = fn_stack.back();
|
||||
frontend_verilog_yyset_lineno(ln_stack.back());
|
||||
}
|
||||
|
||||
"`file_notfound "[^\n]* {
|
||||
log_error("Can't open include file `%s'!\n", yytext + 15);
|
||||
}
|
||||
|
||||
"`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
|
||||
|
||||
"`yosys_enable_defattr" lexer_feature_defattr = true;
|
||||
"`yosys_disable_defattr" lexer_feature_defattr = false;
|
||||
|
||||
"`"[a-zA-Z_$][a-zA-Z0-9_$]* {
|
||||
frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
|
||||
}
|
||||
|
||||
"module" { return TOK_MODULE; }
|
||||
"endmodule" { return TOK_ENDMODULE; }
|
||||
"function" { return TOK_FUNCTION; }
|
||||
"endfunction" { return TOK_ENDFUNCTION; }
|
||||
"task" { return TOK_TASK; }
|
||||
"endtask" { return TOK_ENDTASK; }
|
||||
"parameter" { return TOK_PARAMETER; }
|
||||
"localparam" { return TOK_LOCALPARAM; }
|
||||
"assign" { return TOK_ASSIGN; }
|
||||
"always" { return TOK_ALWAYS; }
|
||||
"initial" { return TOK_INITIAL; }
|
||||
"begin" { return TOK_BEGIN; }
|
||||
"end" { return TOK_END; }
|
||||
"if" { return TOK_IF; }
|
||||
"else" { return TOK_ELSE; }
|
||||
"for" { return TOK_FOR; }
|
||||
"posedge" { return TOK_POSEDGE; }
|
||||
"negedge" { return TOK_NEGEDGE; }
|
||||
"or" { return TOK_OR; }
|
||||
"case" { return TOK_CASE; }
|
||||
"casex" { return TOK_CASEX; }
|
||||
"casez" { return TOK_CASEZ; }
|
||||
"endcase" { return TOK_ENDCASE; }
|
||||
"default" { return TOK_DEFAULT; }
|
||||
"generate" { return TOK_GENERATE; }
|
||||
"endgenerate" { return TOK_ENDGENERATE; }
|
||||
|
||||
"input" { return TOK_INPUT; }
|
||||
"output" { return TOK_OUTPUT; }
|
||||
"inout" { return TOK_INOUT; }
|
||||
"wire" { return TOK_WIRE; }
|
||||
"reg" { return TOK_REG; }
|
||||
"integer" { return TOK_INTEGER; }
|
||||
"signed" { return TOK_SIGNED; }
|
||||
"genvar" { return TOK_GENVAR; }
|
||||
|
||||
[0-9]+ {
|
||||
frontend_verilog_yylval.string = new std::string(yytext);
|
||||
return TOK_CONST;
|
||||
}
|
||||
|
||||
[0-9]*[ \t]*\'s?[bodh][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
|
||||
frontend_verilog_yylval.string = new std::string(yytext);
|
||||
return TOK_CONST;
|
||||
}
|
||||
|
||||
\" { BEGIN(STRING); }
|
||||
<STRING>\\. { yymore(); }
|
||||
<STRING>\" {
|
||||
BEGIN(0);
|
||||
char *yystr = strdup(yytext);
|
||||
yystr[strlen(yytext) - 1] = 0;
|
||||
int i = 0, j = 0;
|
||||
while (yystr[i]) {
|
||||
if (yystr[i] == '\\' && yystr[i + 1]) {
|
||||
i++;
|
||||
if (yystr[i] == 'n')
|
||||
yystr[i] = '\n';
|
||||
else if (yystr[i] == 't')
|
||||
yystr[i] = '\t';
|
||||
else if ('0' <= yystr[i] && yystr[i] <= '7') {
|
||||
yystr[i] = yystr[i] - '0';
|
||||
if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
|
||||
yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
|
||||
i++;
|
||||
}
|
||||
if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
|
||||
yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
|
||||
i++;
|
||||
}
|
||||
}
|
||||
}
|
||||
yystr[j++] = yystr[i++];
|
||||
}
|
||||
yystr[j] = 0;
|
||||
frontend_verilog_yylval.string = new std::string(yystr);
|
||||
free(yystr);
|
||||
return TOK_STRING;
|
||||
}
|
||||
<STRING>. { yymore(); }
|
||||
|
||||
and|nand|or|nor|xor|xnor|not|buf {
|
||||
frontend_verilog_yylval.string = new std::string(yytext);
|
||||
return TOK_PRIMITIVE;
|
||||
}
|
||||
|
||||
supply0 { return TOK_SUPPLY0; }
|
||||
supply1 { return TOK_SUPPLY1; }
|
||||
|
||||
"$"(display|time|stop|finish) {
|
||||
frontend_verilog_yylval.string = new std::string(yytext);
|
||||
return TOK_ID;
|
||||
}
|
||||
|
||||
"$signed" { return TOK_TO_SIGNED; }
|
||||
"$unsigned" { return TOK_TO_UNSIGNED; }
|
||||
|
||||
[a-zA-Z_$][a-zA-Z0-9_$]* {
|
||||
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
|
||||
return TOK_ID;
|
||||
}
|
||||
|
||||
"/*"[ \t]*synopsys[ \t]*translate_off[ \t]*"*/" {
|
||||
log("Warning: Found one of those horrible `synopsys translate_off' comments.\n");
|
||||
log("It is strongly suggested to use `ifdef constructs instead!\n");
|
||||
BEGIN(SYNOPSYS_TRANSLATE_OFF);
|
||||
}
|
||||
<SYNOPSYS_TRANSLATE_OFF>. /* ignore synopsys translate_off body */
|
||||
<SYNOPSYS_TRANSLATE_OFF>\n /* ignore synopsys translate_off body */
|
||||
<SYNOPSYS_TRANSLATE_OFF>"/*"[ \t]*"synopsys"[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); }
|
||||
|
||||
"/*"[ \t]*"synopsys"[ \t]+ {
|
||||
BEGIN(SYNOPSYS_FLAGS);
|
||||
}
|
||||
<SYNOPSYS_FLAGS>full_case {
|
||||
log("Warning: Found one of those horrible `synopsys full_case' comments.\n");
|
||||
log("It is strongly suggested to use verilog x-values and default branches instead!\n");
|
||||
return TOK_SYNOPSYS_FULL_CASE;
|
||||
}
|
||||
<SYNOPSYS_FLAGS>parallel_case {
|
||||
log("Warning: Found one of those horrible `synopsys parallel_case' comments.\n");
|
||||
log("It is strongly suggested to use verilog `parallel_case' attributes instead!\n");
|
||||
return TOK_SYNOPSYS_PARALLEL_CASE;
|
||||
}
|
||||
<SYNOPSYS_FLAGS>. /* ignore everything else */
|
||||
<SYNOPSYS_FLAGS>"*/" { BEGIN(0); }
|
||||
|
||||
"\\"[^ \t\r\n]+ {
|
||||
frontend_verilog_yylval.string = new std::string(yytext);
|
||||
return TOK_ID;
|
||||
}
|
||||
|
||||
"(*" { return ATTR_BEGIN; }
|
||||
"*)" { return ATTR_END; }
|
||||
|
||||
"{*" { if (lexer_feature_defattr) return DEFATTR_BEGIN; else REJECT; }
|
||||
"*}" { if (lexer_feature_defattr) return DEFATTR_END; else REJECT; }
|
||||
|
||||
"**" { return OP_POW; }
|
||||
"||" { return OP_LOR; }
|
||||
"&&" { return OP_LAND; }
|
||||
"==" { return OP_EQ; }
|
||||
"!=" { return OP_NE; }
|
||||
"<=" { return OP_LE; }
|
||||
">=" { return OP_GE; }
|
||||
|
||||
/* "~&" { return OP_NAND; } */
|
||||
/* "~|" { return OP_NOR; } */
|
||||
"~^" { return OP_XNOR; }
|
||||
"^~" { return OP_XNOR; }
|
||||
|
||||
"<<" { return OP_SHL; }
|
||||
">>" { return OP_SHR; }
|
||||
"<<<" { return OP_SSHL; }
|
||||
">>>" { return OP_SSHR; }
|
||||
|
||||
"/*" { BEGIN(COMMENT); }
|
||||
<COMMENT>. /* ignore comment body */
|
||||
<COMMENT>\n /* ignore comment body */
|
||||
<COMMENT>"*/" { BEGIN(0); }
|
||||
|
||||
[ \t\r\n] /* ignore whitespaces */
|
||||
\\[\r\n] /* ignore continuation sequence */
|
||||
"//"[^\r\n]* /* ignore one-line comments */
|
||||
"#"[$a-zA-Z_0-9\.]+ /* ignore simulation timings */
|
||||
|
||||
. { return *yytext; }
|
||||
|
||||
%%
|
||||
|
||||
// this is a hack to avoid the 'yyinput defined but not used' error msgs
|
||||
void *frontend_verilog_avoid_input_warnings() {
|
||||
return (void*)&yyinput;
|
||||
}
|
||||
|
||||
1074
frontends/verilog/parser.y
Normal file
1074
frontends/verilog/parser.y
Normal file
File diff suppressed because it is too large
Load diff
360
frontends/verilog/preproc.cc
Normal file
360
frontends/verilog/preproc.cc
Normal file
|
|
@ -0,0 +1,360 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* ---
|
||||
*
|
||||
* The Verilog frontend.
|
||||
*
|
||||
* This frontend is using the AST frontend library (see frontends/ast/).
|
||||
* Thus this frontend does not generate RTLIL code directly but creates an
|
||||
* AST directly from the Verilog parse tree and then passes this AST to
|
||||
* the AST frontend library.
|
||||
*
|
||||
* ---
|
||||
*
|
||||
* Ad-hoc implementation of a Verilog preprocessor. The directives `define,
|
||||
* `include, `ifdef, `ifndef, `else and `endif are handled here. All other
|
||||
* directives are handled by the lexer (see lexer.l).
|
||||
*
|
||||
*/
|
||||
|
||||
#include "verilog_frontend.h"
|
||||
#include "kernel/log.h"
|
||||
#include <stdarg.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
#include <list>
|
||||
|
||||
static std::list<std::string> output_code;
|
||||
static std::list<std::string> input_buffer;
|
||||
static size_t input_buffer_charp;
|
||||
|
||||
static void return_char(char ch)
|
||||
{
|
||||
if (input_buffer_charp == 0)
|
||||
input_buffer.push_front(std::string() + ch);
|
||||
else
|
||||
input_buffer.front()[--input_buffer_charp] = ch;
|
||||
}
|
||||
|
||||
static void insert_input(std::string str)
|
||||
{
|
||||
if (input_buffer_charp != 0) {
|
||||
input_buffer.front() = input_buffer.front().substr(input_buffer_charp);
|
||||
input_buffer_charp = 0;
|
||||
}
|
||||
input_buffer.push_front(str);
|
||||
}
|
||||
|
||||
static char next_char()
|
||||
{
|
||||
if (input_buffer.size() == 0)
|
||||
return 0;
|
||||
|
||||
assert(input_buffer_charp <= input_buffer.front().size());
|
||||
if (input_buffer_charp == input_buffer.front().size()) {
|
||||
input_buffer_charp = 0;
|
||||
input_buffer.pop_front();
|
||||
return next_char();
|
||||
}
|
||||
|
||||
char ch = input_buffer.front()[input_buffer_charp++];
|
||||
return ch == '\r' ? next_char() : ch;
|
||||
}
|
||||
|
||||
static void skip_spaces()
|
||||
{
|
||||
while (1) {
|
||||
char ch = next_char();
|
||||
if (ch == 0)
|
||||
break;
|
||||
if (ch != ' ' && ch != '\t') {
|
||||
return_char(ch);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static std::string next_token(bool pass_newline = false)
|
||||
{
|
||||
std::string token;
|
||||
|
||||
char ch = next_char();
|
||||
if (ch == 0)
|
||||
return token;
|
||||
|
||||
token += ch;
|
||||
if (ch == '\n') {
|
||||
if (pass_newline) {
|
||||
output_code.push_back(token);
|
||||
return "";
|
||||
}
|
||||
return token;
|
||||
}
|
||||
|
||||
if (ch == ' ' || ch == '\t')
|
||||
{
|
||||
while ((ch = next_char()) != 0) {
|
||||
if (ch != ' ' && ch != '\t') {
|
||||
return_char(ch);
|
||||
break;
|
||||
}
|
||||
token += ch;
|
||||
}
|
||||
}
|
||||
else if (ch == '"')
|
||||
{
|
||||
while ((ch = next_char()) != 0) {
|
||||
token += ch;
|
||||
if (ch == '"')
|
||||
break;
|
||||
if (ch == '\\') {
|
||||
if ((ch = next_char()) != 0)
|
||||
token += ch;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (ch == '/')
|
||||
{
|
||||
if ((ch = next_char()) != 0) {
|
||||
if (ch == '/') {
|
||||
token += '*';
|
||||
char last_ch = 0;
|
||||
while ((ch = next_char()) != 0) {
|
||||
if (ch == '\n') {
|
||||
return_char(ch);
|
||||
break;
|
||||
}
|
||||
if (last_ch != '*' || ch != '/') {
|
||||
token += ch;
|
||||
last_ch = ch;
|
||||
}
|
||||
}
|
||||
token += " */";
|
||||
}
|
||||
else if (ch == '*') {
|
||||
token += '*';
|
||||
int newline_count = 0;
|
||||
char last_ch = 0;
|
||||
while ((ch = next_char()) != 0) {
|
||||
if (ch == '\n') {
|
||||
newline_count++;
|
||||
token += ' ';
|
||||
} else
|
||||
token += ch;
|
||||
if (last_ch == '*' && ch == '/')
|
||||
break;
|
||||
last_ch = ch;
|
||||
}
|
||||
while (newline_count-- > 0)
|
||||
return_char('\n');
|
||||
}
|
||||
else
|
||||
return_char(ch);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
const char *ok = "abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789";
|
||||
while ((ch = next_char()) != 0) {
|
||||
if (strchr(ok, ch) == NULL) {
|
||||
return_char(ch);
|
||||
break;
|
||||
}
|
||||
token += ch;
|
||||
}
|
||||
}
|
||||
|
||||
return token;
|
||||
}
|
||||
|
||||
static void input_file(FILE *f, std::string filename)
|
||||
{
|
||||
char buffer[513];
|
||||
int rc;
|
||||
|
||||
insert_input("");
|
||||
auto it = input_buffer.begin();
|
||||
|
||||
input_buffer.insert(it, "`file_push " + filename + "\n");
|
||||
while ((rc = fread(buffer, 1, sizeof(buffer)-1, f)) > 0) {
|
||||
buffer[rc] = 0;
|
||||
input_buffer.insert(it, buffer);
|
||||
}
|
||||
input_buffer.insert(it, "`file_pop\n");
|
||||
}
|
||||
|
||||
static std::string define_to_feature(std::string defname)
|
||||
{
|
||||
if (defname == "__YOSYS_ENABLE_DEFATTR__")
|
||||
return "defattr";
|
||||
return std::string();
|
||||
}
|
||||
|
||||
std::string frontend_verilog_preproc(FILE *f, std::string filename)
|
||||
{
|
||||
std::map<std::string, std::string> defines_map;
|
||||
int ifdef_fail_level = 0;
|
||||
|
||||
output_code.clear();
|
||||
input_buffer.clear();
|
||||
input_buffer_charp = 0;
|
||||
|
||||
input_file(f, filename);
|
||||
defines_map["__YOSYS__"] = "1";
|
||||
|
||||
while (!input_buffer.empty())
|
||||
{
|
||||
std::string tok = next_token();
|
||||
// printf("token: >>%s<<\n", tok != "\n" ? tok.c_str() : "NEWLINE");
|
||||
|
||||
if (tok == "`endif") {
|
||||
if (ifdef_fail_level > 0)
|
||||
ifdef_fail_level--;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tok == "`else") {
|
||||
if (ifdef_fail_level == 0)
|
||||
ifdef_fail_level = 1;
|
||||
else if (ifdef_fail_level == 1)
|
||||
ifdef_fail_level = 0;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tok == "`ifdef") {
|
||||
skip_spaces();
|
||||
std::string name = next_token(true);
|
||||
if (ifdef_fail_level > 0 || defines_map.count(name) == 0)
|
||||
ifdef_fail_level++;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tok == "`ifndef") {
|
||||
skip_spaces();
|
||||
std::string name = next_token(true);
|
||||
if (ifdef_fail_level > 0 || defines_map.count(name) != 0)
|
||||
ifdef_fail_level++;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (ifdef_fail_level > 0) {
|
||||
if (tok == "\n")
|
||||
output_code.push_back(tok);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tok == "`include") {
|
||||
skip_spaces();
|
||||
std::string fn = next_token(true);
|
||||
while (1) {
|
||||
size_t pos = fn.find('"');
|
||||
if (pos == std::string::npos)
|
||||
break;
|
||||
if (pos == 0)
|
||||
fn = fn.substr(1);
|
||||
else
|
||||
fn = fn.substr(0, pos) + fn.substr(pos+1);
|
||||
}
|
||||
FILE *fp = fopen(fn.c_str(), "r");
|
||||
if (fp == NULL && fn.size() > 0 && fn[0] != '/' && filename.find('/') != std::string::npos) {
|
||||
std::string fn2 = filename.substr(0, filename.rfind('/')+1) + fn;
|
||||
fp = fopen(fn2.c_str(), "r");
|
||||
}
|
||||
if (fp != NULL) {
|
||||
input_file(fp, fn);
|
||||
fclose(fp);
|
||||
} else
|
||||
output_code.push_back("`file_notfound " + fn + "\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tok == "`define") {
|
||||
std::string name, value;
|
||||
skip_spaces();
|
||||
name = next_token(true);
|
||||
if (!define_to_feature(name).empty())
|
||||
output_code.push_back("`yosys_enable_" + define_to_feature(name));
|
||||
skip_spaces();
|
||||
int newline_count = 0;
|
||||
while (!tok.empty()) {
|
||||
tok = next_token();
|
||||
if (tok == "\n") {
|
||||
return_char('\n');
|
||||
break;
|
||||
}
|
||||
if (tok == "\\") {
|
||||
char ch = next_char();
|
||||
if (ch == '\n') {
|
||||
value += " ";
|
||||
newline_count++;
|
||||
} else {
|
||||
value += std::string("\\");
|
||||
return_char(ch);
|
||||
}
|
||||
} else
|
||||
value += tok;
|
||||
}
|
||||
while (newline_count-- > 0)
|
||||
return_char('\n');
|
||||
// printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str());
|
||||
defines_map[name] = value;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tok == "`undef") {
|
||||
std::string name;
|
||||
skip_spaces();
|
||||
name = next_token(true);
|
||||
if (!define_to_feature(name).empty())
|
||||
output_code.push_back("`yosys_disable_" + define_to_feature(name));
|
||||
// printf("undef: >>%s<<\n", name.c_str());
|
||||
defines_map.erase(name);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tok == "`timescale") {
|
||||
std::string name;
|
||||
skip_spaces();
|
||||
while (!tok.empty() && tok != "\n")
|
||||
tok = next_token(true);
|
||||
if (tok == "\n")
|
||||
return_char('\n');
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tok.size() > 1 && tok[0] == '`' && defines_map.count(tok.substr(1)) > 0) {
|
||||
// printf("expand: >>%s<< -> >>%s<<\n", tok.c_str(), defines_map[tok.substr(1)].c_str());
|
||||
insert_input(defines_map[tok.substr(1)]);
|
||||
continue;
|
||||
}
|
||||
|
||||
output_code.push_back(tok);
|
||||
}
|
||||
|
||||
std::string output;
|
||||
for (auto &str : output_code)
|
||||
output += str;
|
||||
|
||||
output_code.clear();
|
||||
input_buffer.clear();
|
||||
input_buffer_charp = 0;
|
||||
|
||||
return output;
|
||||
}
|
||||
|
||||
148
frontends/verilog/verilog_frontend.cc
Normal file
148
frontends/verilog/verilog_frontend.cc
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* ---
|
||||
*
|
||||
* The Verilog frontend.
|
||||
*
|
||||
* This frontend is using the AST frontend library (see frontends/ast/).
|
||||
* Thus this frontend does not generate RTLIL code directly but creates an
|
||||
* AST directly from the Verilog parse tree and then passes this AST to
|
||||
* the AST frontend library.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "verilog_frontend.h"
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/log.h"
|
||||
#include "kernel/sha1.h"
|
||||
#include <sstream>
|
||||
#include <stdarg.h>
|
||||
#include <assert.h>
|
||||
|
||||
using namespace VERILOG_FRONTEND;
|
||||
|
||||
// use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
|
||||
|
||||
struct VerilogFrontend : public Frontend {
|
||||
VerilogFrontend() : Frontend("verilog") { }
|
||||
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
|
||||
{
|
||||
bool flag_dump_ast = false;
|
||||
bool flag_dump_ast_diff = false;
|
||||
bool flag_dump_vlog = false;
|
||||
bool flag_nolatches = false;
|
||||
bool flag_nomem2reg = false;
|
||||
bool flag_ppdump = false;
|
||||
bool flag_nopp = false;
|
||||
frontend_verilog_yydebug = false;
|
||||
|
||||
log_header("Executing Verilog-2005 frontend.\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
std::string arg = args[argidx];
|
||||
if (arg == "-dump_ast") {
|
||||
flag_dump_ast = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-dump_ast_diff") {
|
||||
flag_dump_ast = true;
|
||||
flag_dump_ast_diff = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-dump_vlog") {
|
||||
flag_dump_vlog = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-yydebug") {
|
||||
frontend_verilog_yydebug = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-nolatches") {
|
||||
flag_nolatches = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-nomem2reg") {
|
||||
flag_nomem2reg = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-ppdump") {
|
||||
flag_ppdump = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-nopp") {
|
||||
flag_nopp = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(f, filename, args, argidx);
|
||||
|
||||
log("Parsing Verilog input from `%s' to AST representation.\n", filename.c_str());
|
||||
|
||||
AST::current_filename = filename;
|
||||
AST::set_line_num = &frontend_verilog_yyset_lineno;
|
||||
AST::get_line_num = &frontend_verilog_yyget_lineno;
|
||||
|
||||
current_ast = new AST::AstNode(AST::AST_DESIGN);
|
||||
|
||||
FILE *fp = f;
|
||||
std::string code_after_preproc;
|
||||
|
||||
if (!flag_nopp) {
|
||||
code_after_preproc = frontend_verilog_preproc(f, filename);
|
||||
if (flag_ppdump)
|
||||
log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
|
||||
fp = fmemopen((void*)code_after_preproc.c_str(), code_after_preproc.size(), "r");
|
||||
}
|
||||
|
||||
lexer_feature_defattr = false;
|
||||
|
||||
frontend_verilog_yyset_lineno(1);
|
||||
frontend_verilog_yyrestart(fp);
|
||||
frontend_verilog_yyparse();
|
||||
frontend_verilog_yylex_destroy();
|
||||
|
||||
AST::process(design, current_ast, flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg);
|
||||
|
||||
if (!flag_nopp)
|
||||
fclose(fp);
|
||||
|
||||
delete current_ast;
|
||||
current_ast = NULL;
|
||||
|
||||
log("Successfully finished Verilog frontend.\n");
|
||||
}
|
||||
} VerilogFrontend;
|
||||
|
||||
// the yyerror function used by bison to report parser errors
|
||||
void frontend_verilog_yyerror(char const *fmt, ...)
|
||||
{
|
||||
va_list ap;
|
||||
char buffer[1024];
|
||||
char *p = buffer;
|
||||
p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ",
|
||||
AST::current_filename.c_str(), frontend_verilog_yyget_lineno());
|
||||
va_start(ap, fmt);
|
||||
p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
|
||||
va_end(ap);
|
||||
p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
|
||||
log_error("%s", buffer);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
62
frontends/verilog/verilog_frontend.h
Normal file
62
frontends/verilog/verilog_frontend.h
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
* ---
|
||||
*
|
||||
* The Verilog frontend.
|
||||
*
|
||||
* This frontend is using the AST frontend library (see frontends/ast/).
|
||||
* Thus this frontend does not generate RTLIL code directly but creates an
|
||||
* AST directly from the Verilog parse tree and then passes this AST to
|
||||
* the AST frontend library.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef VERILOG_FRONTEND_H
|
||||
#define VERILOG_FRONTEND_H
|
||||
|
||||
#include "kernel/rtlil.h"
|
||||
#include "frontends/ast/ast.h"
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
|
||||
namespace VERILOG_FRONTEND
|
||||
{
|
||||
// this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser
|
||||
extern struct AST::AstNode *current_ast;
|
||||
|
||||
// this function converts a Verilog constant to an AST_CONSTANT node
|
||||
AST::AstNode *const2ast(std::string code, char case_type = 0);
|
||||
|
||||
// lexer state variables
|
||||
extern bool lexer_feature_defattr;
|
||||
}
|
||||
|
||||
// the pre-processor
|
||||
std::string frontend_verilog_preproc(FILE *f, std::string filename);
|
||||
|
||||
// the usual bison/flex stuff
|
||||
extern int frontend_verilog_yydebug;
|
||||
int frontend_verilog_yylex(void);
|
||||
void frontend_verilog_yyerror(char const *fmt, ...);
|
||||
void frontend_verilog_yyrestart(FILE *f);
|
||||
int frontend_verilog_yyparse(void);
|
||||
int frontend_verilog_yylex_destroy(void);
|
||||
int frontend_verilog_yyget_lineno(void);
|
||||
void frontend_verilog_yyset_lineno (int);
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue