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https://github.com/YosysHQ/yosys
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initial import
This commit is contained in:
Clifford Wolf
commit
7764d0ba1d
481 changed files with 54634 additions and 0 deletions
306
backends/ilang/ilang_backend.cc
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306
backends/ilang/ilang_backend.cc
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* A very simple and straightforward backend for the RTLIL text
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* representation (as understood by the 'ilang' frontend).
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*
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*/
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#include "ilang_backend.h"
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <string>
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#include <assert.h>
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using namespace ILANG_BACKEND;
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void ILANG_BACKEND::dump_const(FILE *f, const RTLIL::Const &data, int width, int offset, bool autoint)
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{
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if (width < 0)
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width = data.bits.size() - offset;
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if (data.str.empty() || width != (int)data.bits.size()) {
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if (width == 32 && autoint) {
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int32_t val = 0;
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for (int i = 0; i < width; i++) {
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assert(offset+i < (int)data.bits.size());
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switch (data.bits[offset+i]) {
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case RTLIL::S0: break;
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case RTLIL::S1: val |= 1 << i; break;
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default: val = -1; break;
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}
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}
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if (val >= 0) {
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fprintf(f, "%d", val);
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return;
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}
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}
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fprintf(f, "%d'", width);
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for (int i = offset+width-1; i >= offset; i--) {
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assert(i < (int)data.bits.size());
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switch (data.bits[i]) {
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case RTLIL::S0: fprintf(f, "0"); break;
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case RTLIL::S1: fprintf(f, "1"); break;
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case RTLIL::Sx: fprintf(f, "x"); break;
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case RTLIL::Sz: fprintf(f, "z"); break;
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case RTLIL::Sa: fprintf(f, "-"); break;
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case RTLIL::Sm: fprintf(f, "m"); break;
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}
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}
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} else {
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fprintf(f, "\"");
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for (size_t i = 0; i < data.str.size(); i++) {
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if (data.str[i] == '\n')
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fprintf(f, "\\n");
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else if (data.str[i] == '\t')
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fprintf(f, "\\t");
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else if (data.str[i] < 32)
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fprintf(f, "\\%03o", data.str[i]);
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else if (data.str[i] == '"')
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fprintf(f, "\\\"");
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else
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fputc(data.str[i], f);
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}
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fprintf(f, "\"");
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}
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}
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void ILANG_BACKEND::dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool autoint)
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{
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if (chunk.wire == NULL) {
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dump_const(f, chunk.data, chunk.width, chunk.offset, autoint);
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} else {
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if (chunk.width == chunk.wire->width && chunk.offset == 0)
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fprintf(f, "%s", chunk.wire->name.c_str());
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else if (chunk.width == 1)
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fprintf(f, "%s [%d]", chunk.wire->name.c_str(), chunk.offset);
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else
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fprintf(f, "%s [%d:%d]", chunk.wire->name.c_str(), chunk.offset+chunk.width-1, chunk.offset);
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}
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}
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void ILANG_BACKEND::dump_sigspec(FILE *f, const RTLIL::SigSpec &sig, bool autoint)
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{
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if (sig.chunks.size() == 1) {
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dump_sigchunk(f, sig.chunks[0], autoint);
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} else {
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fprintf(f, "{ ");
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for (auto it = sig.chunks.rbegin(); it != sig.chunks.rend(); it++) {
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dump_sigchunk(f, *it, false);
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fprintf(f, " ");
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}
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fprintf(f, "}");
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}
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}
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void ILANG_BACKEND::dump_wire(FILE *f, std::string indent, const RTLIL::Wire *wire)
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{
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for (auto it = wire->attributes.begin(); it != wire->attributes.end(); it++) {
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fprintf(f, "%s" "attribute %s ", indent.c_str(), it->first.c_str());
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dump_const(f, it->second);
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fprintf(f, "\n");
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}
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fprintf(f, "%s" "wire ", indent.c_str());
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if (wire->auto_width)
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fprintf(f, "auto ");
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if (wire->width != 1)
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fprintf(f, "width %d ", wire->width);
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if (wire->start_offset != 0)
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fprintf(f, "offset %d ", wire->start_offset);
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if (wire->port_input && !wire->port_output)
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fprintf(f, "input %d ", wire->port_id);
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if (!wire->port_input && wire->port_output)
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fprintf(f, "output %d ", wire->port_id);
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if (wire->port_input && wire->port_output)
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fprintf(f, "inout %d ", wire->port_id);
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fprintf(f, "%s\n", wire->name.c_str());
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}
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void ILANG_BACKEND::dump_memory(FILE *f, std::string indent, const RTLIL::Memory *memory)
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{
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for (auto it = memory->attributes.begin(); it != memory->attributes.end(); it++) {
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fprintf(f, "%s" "attribute %s ", indent.c_str(), it->first.c_str());
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dump_const(f, it->second);
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fprintf(f, "\n");
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}
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fprintf(f, "%s" "memory ", indent.c_str());
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if (memory->width != 1)
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fprintf(f, "width %d ", memory->width);
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if (memory->size != 0)
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fprintf(f, "size %d ", memory->size);
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fprintf(f, "%s\n", memory->name.c_str());
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}
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void ILANG_BACKEND::dump_cell(FILE *f, std::string indent, const RTLIL::Cell *cell)
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{
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for (auto it = cell->attributes.begin(); it != cell->attributes.end(); it++) {
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fprintf(f, "%s" "attribute %s ", indent.c_str(), it->first.c_str());
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dump_const(f, it->second);
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fprintf(f, "\n");
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}
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fprintf(f, "%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str());
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for (auto it = cell->parameters.begin(); it != cell->parameters.end(); it++) {
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fprintf(f, "%s parameter %s ", indent.c_str(), it->first.c_str());
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dump_const(f, it->second);
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fprintf(f, "\n");
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}
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for (auto it = cell->connections.begin(); it != cell->connections.end(); it++) {
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fprintf(f, "%s connect %s ", indent.c_str(), it->first.c_str());
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dump_sigspec(f, it->second);
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fprintf(f, "\n");
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}
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fprintf(f, "%s" "end\n", indent.c_str());
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}
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void ILANG_BACKEND::dump_proc_case_body(FILE *f, std::string indent, const RTLIL::CaseRule *cs)
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{
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for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
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{
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fprintf(f, "%s" "assign ", indent.c_str());
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dump_sigspec(f, it->first);
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fprintf(f, " ");
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dump_sigspec(f, it->second);
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fprintf(f, "\n");
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}
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for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
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dump_proc_switch(f, indent, *it);
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}
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void ILANG_BACKEND::dump_proc_switch(FILE *f, std::string indent, const RTLIL::SwitchRule *sw)
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{
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for (auto it = sw->attributes.begin(); it != sw->attributes.end(); it++) {
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fprintf(f, "%s" "attribute %s ", indent.c_str(), it->first.c_str());
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dump_const(f, it->second);
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fprintf(f, "\n");
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}
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fprintf(f, "%s" "switch ", indent.c_str());
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dump_sigspec(f, sw->signal);
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fprintf(f, "\n");
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for (auto it = sw->cases.begin(); it != sw->cases.end(); it++)
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{
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fprintf(f, "%s case ", indent.c_str());
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for (size_t i = 0; i < (*it)->compare.size(); i++) {
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if (i > 0)
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fprintf(f, ", ");
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dump_sigspec(f, (*it)->compare[i]);
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}
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fprintf(f, "\n");
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dump_proc_case_body(f, indent + " ", *it);
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}
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fprintf(f, "%s" "end\n", indent.c_str());
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}
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void ILANG_BACKEND::dump_proc_sync(FILE *f, std::string indent, const RTLIL::SyncRule *sy)
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{
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fprintf(f, "%s" "sync ", indent.c_str());
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switch (sy->type) {
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if (0) case RTLIL::ST0: fprintf(f, "low ");
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if (0) case RTLIL::ST1: fprintf(f, "high ");
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if (0) case RTLIL::STp: fprintf(f, "posedge ");
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if (0) case RTLIL::STn: fprintf(f, "negedge ");
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if (0) case RTLIL::STe: fprintf(f, "edge ");
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dump_sigspec(f, sy->signal);
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fprintf(f, "\n");
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break;
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case RTLIL::STa: fprintf(f, "always\n"); break;
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}
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for (auto it = sy->actions.begin(); it != sy->actions.end(); it++) {
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fprintf(f, "%s update ", indent.c_str());
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dump_sigspec(f, it->first);
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fprintf(f, " ");
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dump_sigspec(f, it->second);
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fprintf(f, "\n");
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}
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}
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void ILANG_BACKEND::dump_proc(FILE *f, std::string indent, const RTLIL::Process *proc)
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{
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for (auto it = proc->attributes.begin(); it != proc->attributes.end(); it++) {
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fprintf(f, "%s" "attribute %s ", indent.c_str(), it->first.c_str());
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dump_const(f, it->second);
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fprintf(f, "\n");
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}
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fprintf(f, "%s" "process %s\n", indent.c_str(), proc->name.c_str());
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dump_proc_case_body(f, indent + " ", &proc->root_case);
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for (auto it = proc->syncs.begin(); it != proc->syncs.end(); it++)
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dump_proc_sync(f, indent + " ", *it);
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fprintf(f, "%s" "end\n", indent.c_str());
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}
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void ILANG_BACKEND::dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
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{
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fprintf(f, "%s" "connect ", indent.c_str());
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dump_sigspec(f, left);
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fprintf(f, " ");
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dump_sigspec(f, right);
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fprintf(f, "\n");
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}
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void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module *module)
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{
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for (auto it = module->attributes.begin(); it != module->attributes.end(); it++) {
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fprintf(f, "%s" "attribute %s ", indent.c_str(), it->first.c_str());
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dump_const(f, it->second);
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fprintf(f, "\n");
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}
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fprintf(f, "%s" "module %s\n", indent.c_str(), module->name.c_str());
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for (auto it = module->wires.begin(); it != module->wires.end(); it++)
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dump_wire(f, indent + " ", it->second);
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for (auto it = module->memories.begin(); it != module->memories.end(); it++)
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dump_memory(f, indent + " ", it->second);
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for (auto it = module->cells.begin(); it != module->cells.end(); it++)
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dump_cell(f, indent + " ", it->second);
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for (auto it = module->processes.begin(); it != module->processes.end(); it++)
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dump_proc(f, indent + " ", it->second);
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for (auto it = module->connections.begin(); it != module->connections.end(); it++)
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dump_conn(f, indent + " ", it->first, it->second);
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fprintf(f, "%s" "end\n", indent.c_str());
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}
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void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design)
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{
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for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
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if (it != design->modules.begin())
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fprintf(f, "\n");
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dump_module(f, "", it->second);
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}
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}
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struct IlangBackend : public Backend {
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IlangBackend() : Backend("ilang") { }
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) {
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log_header("Executing ILANG backend.\n");
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extra_args(f, filename, args, 1);
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log("Output filename: %s\n", filename.c_str());
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ILANG_BACKEND::dump_design(f, design);
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}
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} IlangBackend;
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