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sta: very crude static timing analysis pass

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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
This commit is contained in:
Lofty 2021-11-24 21:21:08 +00:00 • committed by Marcelina Kościelnicka
parent 113c943841
commit 77327b2544
9 changed files with 503 additions and 63 deletions
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81
tests/various/sta.ys Normal file
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read_verilog -specify <<EOT
module buffer(input i, output o);
specify
(i => o) = 10;
endspecify
endmodule
module top(input i);
wire w;
buffer b(.i(i), .o(w));
endmodule
EOT
logger -expect warning "Critical-path does not terminate in a recognised endpoint\." 1
sta
design -reset
read_verilog -specify <<EOT
module top(input i, output o, p);
assign o = i;
endmodule
EOT
logger -expect log "No timing paths found\." 1
sta
design -reset
read_verilog -specify <<EOT
module buffer(input i, output o);
specify
(i => o) = 10;
endspecify
endmodule
module top(input i, output o, p);
buffer b(.i(i), .o(o));
endmodule
EOT
sta
design -reset
read_verilog -specify <<EOT
module buffer(input i, output o);
specify
(i => o) = 10;
endspecify
endmodule
module top(input i, output o, p);
buffer b(.i(i), .o(o));
const0 c(.o(p));
endmodule
EOT
logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1
sta
design -reset
read_verilog -specify <<EOT
module buffer(input i, output o);
specify
(i => o) = 10;
endspecify
endmodule
module const0(output o);
endmodule
module top(input i, output o, p);
buffer b(.i(i), .o(o));
const0 c(.o(p));
endmodule
EOT
sta
logger -expect-no-warnings