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sta: very crude static timing analysis pass

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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
This commit is contained in:
Lofty 2021-11-24 21:21:08 +00:00 • committed by Marcelina Kościelnicka
parent 113c943841
commit 77327b2544
9 changed files with 503 additions and 63 deletions
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60
passes/techmap/abc9_ops.cc
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@ -648,40 +648,38 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
auto inst_module = design->module(cell->type);
log_assert(inst_module);
auto &t = timing.at(cell->type).required;
for (auto &conn : cell->connections_) {
auto port_wire = inst_module->wire(conn.first);
for (auto &i : timing.at(cell->type).required) {
auto port_wire = inst_module->wire(i.first.name);
if (!port_wire)
log_error("Port %s in cell %s (type %s) from module %s does not actually exist",
log_id(conn.first), log_id(cell), log_id(cell->type), log_id(module));
if (!port_wire->port_input)
continue;
if (conn.second.is_fully_const())
log_id(i.first.name), log_id(cell), log_id(cell->type), log_id(module));
log_assert(port_wire->port_input);
auto d = i.second.first;
if (d == 0)
continue;
SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
for (int i = 0; i < GetSize(conn.second); i++) {
auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
if (d == 0)
continue;
auto offset = i.first.offset;
auto O = module->addWire(NEW_ID);
auto rhs = cell->getPort(i.first.name);
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::tuple<IdString,IdString,int>> seen;
if (seen.emplace(cell->type, conn.first, i).second) log("%s.%s[%d] abc9_required = %d\n",
log_id(cell->type), log_id(conn.first), i, d);
}
#endif
auto r = box_cache.insert(d);
if (r.second) {
r.first->second = delay_module->derive(design, {{ID::DELAY, d}});
log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
}
auto box = module->addCell(NEW_ID, r.first->second);
box->setPort(ID::I, conn.second[i]);
box->setPort(ID::O, O[i]);
conn.second[i] = O[i];
if (ys_debug(1)) {
static pool<std::pair<IdString,TimingInfo::NameBit>> seen;
if (seen.emplace(cell->type, i.first).second) log("%s.%s[%d] abc9_required = %d\n",
log_id(cell->type), log_id(i.first.name), offset, d);
}
#endif
auto r = box_cache.insert(d);
if (r.second) {
r.first->second = delay_module->derive(design, {{ID::DELAY, d}});
log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
}
auto box = module->addCell(NEW_ID, r.first->second);
box->setPort(ID::I, rhs[offset]);
box->setPort(ID::O, O);
rhs[offset] = O;
cell->setPort(i.first.name, rhs);
}
}
}
@ -1006,16 +1004,16 @@ void prep_box(RTLIL::Design *design)
log_assert(GetSize(wire) == 1);
auto it = t.find(TimingInfo::NameBit(port_name,0));
if (it == t.end())
// Assume no connectivity if no setup time
ss << "-";
// Assume that no setup time means zero
ss << 0;
else {
ss << it->second;
ss << it->second.first;
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::pair<IdString,IdString>> seen;
if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
log_id(port_name), it->second);
log_id(port_name), it->second.first);
}
#endif
}