From 772d821fb0f68bcf0c2baf321ebd1aa64965fe42 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 19 Dec 2025 18:30:17 +0100
Subject: [PATCH] opt_expr: reindent test

---
 tests/opt/opt_expr_combined_assign.ys | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys
index b18923c7b..f84978a0a 100644
--- a/tests/opt/opt_expr_combined_assign.ys
+++ b/tests/opt/opt_expr_combined_assign.ys
@@ -5,7 +5,7 @@ initial begin
 	a |= i;
 	a |= j;
 end
-    assign o = a;
+	assign o = a;
 endmodule
 EOT
 proc
@@ -19,10 +19,10 @@ read_verilog -sv <<EOT
 module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
 wire[8:0] a = 8'b0;
 initial begin
-        a += i;
-        a += j;
+	a += i;
+	a += j;
 end
-    assign o = a;
+	assign o = a;
 endmodule
 EOT
 proc
@@ -36,10 +36,10 @@ read_verilog -sv <<EOT
 module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
 wire[8:0] a = 8'b0;
 initial begin
-        a ^= i;
-        a ^= j;
+	a ^= i;
+	a ^= j;
 end
-    assign o = a;
+	assign o = a;
 endmodule
 EOT
 proc
@@ -53,10 +53,10 @@ read_verilog -sv <<EOT
 module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
 wire[8:0] a = 8'b0;
 initial begin
-        a -= i;
-        a -= j;
+	a -= i;
+	a -= j;
 end
-    assign o = a;
+	assign o = a;
 endmodule
 EOT
 proc
@@ -70,10 +70,10 @@ read_verilog -sv <<EOT
 module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
 wire[8:0] a = 8'b11111111;
 initial begin
-        a &= i;
-        a &= j;
+	a &= i;
+	a &= j;
 end
-    assign o = a;
+	assign o = a;
 endmodule
 EOT
 proc