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code cleanup

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williamzhu17 2025-03-27 15:27:15 -07:00
parent eefdcbfe81
commit 770eecb4f7
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tests/silimate/mux_ornot.ys
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@ -71,9 +71,7 @@ equiv_opt -assert opt_expr -mux_bool
# Check final design has correct number of gates
# Did not include check for not count since we have an unassigned ~s wire
# TODO check
design -load postopt
write_verilog dump.v
select -assert-count 1 t:$or
design -reset