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rename: add -move-to-cell option in -wire mode

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Jannis Harder 2025-05-07 12:22:37 +02:00 • committed by Emil J. Tywoniak
parent fb024c4d55
commit 77089a8d03
2 changed files with 80 additions and 9 deletions
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35
tests/various/rename_wire_move_to_cell.ys Normal file
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@ -0,0 +1,35 @@
read_verilog <<EOF
module top(input clk, rst, input [7:0] din, output [7:0] dout, input bin, output bout);
reg [7:0] dq;
reg bq;
always @(posedge clk, posedge rst) begin
if (rst) dq <= '0;
else dq <= din;
end
always @(posedge clk) bq <= bin;
assign dout = dq;
assign bout = bq;
endmodule
EOF
proc
hierarchy -top top
select -assert-count 1 t:$dff
select -assert-count 1 t:$adff
select -assert-count 0 t:$dff n:bq %i
select -assert-count 0 t:$adff n:dq %i
select -assert-count 1 w:bq
select -assert-count 1 w:dq
rename -wire -move-to-cell
select -assert-count 1 t:$dff
select -assert-count 1 t:$adff
select -assert-count 1 t:$dff n:bq %i
select -assert-count 1 t:$adff n:dq %i
select -assert-count 0 w:bq
select -assert-count 0 w:dq