3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00

Added support for multiple clock domains to "abc" pass

This commit is contained in:
Clifford Wolf 2014-12-21 16:52:05 +01:00
parent 25844b5683
commit 76fa527492
2 changed files with 124 additions and 64 deletions

View file

@ -1017,6 +1017,7 @@ public:
inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }
inline int size() const { return width_; }
inline bool empty() const { return width_ == 0; }
inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }
inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }