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https://github.com/YosysHQ/yosys
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Using simplemap mappers from techmap
This commit is contained in:
Clifford Wolf
parent
3ee33cbdaf
commit
76f7c10cfc
3 changed files with 104 additions and 742 deletions
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@ -25,6 +25,8 @@
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#include <stdio.h>
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#include <string.h>
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extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
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static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\Y_WIDTH").as_int();
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@ -448,6 +450,30 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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}
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void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
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{
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mappers["$not"] = simplemap_not;
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mappers["$pos"] = simplemap_pos;
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mappers["$and"] = simplemap_bitop;
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mappers["$or"] = simplemap_bitop;
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mappers["$xor"] = simplemap_bitop;
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mappers["$xnor"] = simplemap_bitop;
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mappers["$reduce_and"] = simplemap_reduce;
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mappers["$reduce_or"] = simplemap_reduce;
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mappers["$reduce_xor"] = simplemap_reduce;
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mappers["$reduce_xnor"] = simplemap_reduce;
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mappers["$reduce_bool"] = simplemap_reduce;
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mappers["$logic_not"] = simplemap_lognot;
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mappers["$logic_and"] = simplemap_logbin;
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mappers["$logic_or"] = simplemap_logbin;
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mappers["$mux"] = simplemap_mux;
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mappers["$sr"] = simplemap_sr;
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mappers["$dff"] = simplemap_dff;
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mappers["$dffsr"] = simplemap_dffsr;
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mappers["$adff"] = simplemap_adff;
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mappers["$dlatch"] = simplemap_dlatch;
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}
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struct SimplemapPass : public Pass {
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SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
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virtual void help()
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@ -470,41 +496,20 @@ struct SimplemapPass : public Pass {
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log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
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extra_args(args, 1, design);
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std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> supported_cells;
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supported_cells["$not"] = simplemap_not;
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supported_cells["$pos"] = simplemap_pos;
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supported_cells["$and"] = simplemap_bitop;
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supported_cells["$or"] = simplemap_bitop;
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supported_cells["$xor"] = simplemap_bitop;
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supported_cells["$xnor"] = simplemap_bitop;
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supported_cells["$reduce_and"] = simplemap_reduce;
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supported_cells["$reduce_or"] = simplemap_reduce;
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supported_cells["$reduce_xor"] = simplemap_reduce;
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supported_cells["$reduce_xnor"] = simplemap_reduce;
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supported_cells["$reduce_bool"] = simplemap_reduce;
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supported_cells["$logic_not"] = simplemap_lognot;
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supported_cells["$logic_and"] = simplemap_logbin;
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supported_cells["$logic_or"] = simplemap_logbin;
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supported_cells["$mux"] = simplemap_mux;
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supported_cells["$sr"] = simplemap_sr;
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supported_cells["$dff"] = simplemap_dff;
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supported_cells["$dffsr"] = simplemap_dffsr;
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supported_cells["$adff"] = simplemap_adff;
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supported_cells["$dlatch"] = simplemap_dlatch;
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std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
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simplemap_get_mappers(mappers);
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for (auto &mod_it : design->modules) {
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if (!design->selected(mod_it.second))
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continue;
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std::vector<RTLIL::Cell*> delete_cells;
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for (auto &cell_it : mod_it.second->cells) {
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auto mapper = supported_cells[cell_it.second->type];
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if (mapper == NULL)
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if (mappers.count(cell_it.second->type) == 0)
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continue;
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if (!design->selected(mod_it.second, cell_it.second))
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continue;
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log("Mapping %s.%s (%s).\n", RTLIL::id2cstr(mod_it.first), RTLIL::id2cstr(cell_it.first), RTLIL::id2cstr(cell_it.second->type));
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mapper(mod_it.second, cell_it.second);
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mappers.at(cell_it.second->type)(mod_it.second, cell_it.second);
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delete_cells.push_back(cell_it.second);
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}
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for (auto &it : delete_cells) {
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@ -27,6 +27,9 @@
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#include "passes/techmap/stdcells.inc"
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// see simplemap.cc
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extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
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static void apply_prefix(std::string prefix, std::string &id)
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{
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if (id[0] == '\\')
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@ -47,6 +50,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
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}
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}
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std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
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std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
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std::map<RTLIL::Module*, bool> techmap_do_cache;
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@ -217,7 +221,20 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
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RTLIL::Module *tpl = map->modules[tpl_name];
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std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
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if (!flatten_mode) {
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if (!flatten_mode)
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{
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if (tpl->get_bool_attribute("\\techmap_simplemap")) {
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log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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if (simplemap_mappers.count(cell->type) == 0)
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log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
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simplemap_mappers.at(cell->type)(module, cell);
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module->cells.erase(cell->name);
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delete cell;
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cell = NULL;
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did_something = true;
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break;
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}
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for (auto conn : cell->connections) {
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if (conn.first.substr(0, 1) == "$")
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continue;
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@ -386,11 +403,15 @@ struct TechmapPass : public Pass {
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log(" '-ignore_redef' option set.\n");
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log("\n");
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log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
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log("match cells with a type that match the text value of this attribute.\n");
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log("match cells with a type that match the text value of this attribute. Otherwise\n");
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log("the module name will be used to match the cell.\n");
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log("\n");
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log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
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log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
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log("\n");
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log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
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log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
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log("the mapping module to the techmap command. At the moment the following spoecial\n");
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log("the mapping module to the techmap command. At the moment the following special\n");
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log("wires are supported:\n");
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log("\n");
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log(" _TECHMAP_FAIL_\n");
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@ -412,6 +433,13 @@ struct TechmapPass : public Pass {
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log(" wire to start out as non-constant and evaluate to a constant value\n");
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log(" during processing of other _TECHMAP_DO_* commands.\n");
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log("\n");
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log("In addition to this special wires, techmap also supports special parameters in\n");
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log("modules in the map file:\n");
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log("\n");
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log(" _TECHMAP_CELLTYPE_\n");
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log(" When a parameter with this name exists, it will be set to the type name\n");
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log(" of the cell that matches the module.\n");
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log("\n");
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log("When a module in the map file has a parameter where the according cell in the\n");
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log("design has a port, the module from the map file is only used if the port in\n");
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log("the design is connected to a constant value. The parameter is then set to the\n");
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@ -453,6 +481,8 @@ struct TechmapPass : public Pass {
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}
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extra_args(args, argidx, design);
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simplemap_get_mappers(simplemap_mappers);
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RTLIL::Design *map = new RTLIL::Design;
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if (map_files.empty()) {
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FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt");
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@ -500,6 +530,7 @@ struct TechmapPass : public Pass {
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log("No more expansions possible.\n");
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techmap_cache.clear();
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techmap_do_cache.clear();
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simplemap_mappers.clear();
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delete map;
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log_pop();
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}
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@ -32,54 +32,14 @@
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// --------------------------------------------------------
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module \$not (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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\$_INV_ gate (
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.A(A_buf[i]),
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.Y(Y[i])
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);
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end
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endgenerate
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(* techmap_simplemap *)
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module \$not ;
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endmodule
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// --------------------------------------------------------
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module \$pos (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output [Y_WIDTH-1:0] Y;
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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if (i < A_WIDTH) begin
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assign Y[i] = A[i];
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end else if (A_SIGNED) begin
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assign Y[i] = A[A_WIDTH-1];
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end else begin
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assign Y[i] = 0;
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end
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end
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endgenerate
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(* techmap_simplemap *)
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module \$pos ;
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endmodule
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// --------------------------------------------------------
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@ -109,286 +69,57 @@ endmodule
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// --------------------------------------------------------
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module \$and (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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\$_AND_ gate (
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.A(A_buf[i]),
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.B(B_buf[i]),
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.Y(Y[i])
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);
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end
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endgenerate
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(* techmap_simplemap *)
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module \$and ;
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endmodule
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// --------------------------------------------------------
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module \$or (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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\$_OR_ gate (
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.A(A_buf[i]),
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.B(B_buf[i]),
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.Y(Y[i])
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);
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end
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endgenerate
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(* techmap_simplemap *)
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module \$or ;
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endmodule
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// --------------------------------------------------------
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module \$xor (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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\$_XOR_ gate (
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.A(A_buf[i]),
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.B(B_buf[i]),
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.Y(Y[i])
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);
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end
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endgenerate
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(* techmap_simplemap *)
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module \$xor ;
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endmodule
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// --------------------------------------------------------
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module \$xnor (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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genvar i;
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generate
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for (i = 0; i < Y_WIDTH; i = i + 1) begin:V
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wire tmp;
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\$_XOR_ gate1 (
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.A(A_buf[i]),
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.B(B_buf[i]),
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.Y(tmp)
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);
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\$_INV_ gate2 (
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.A(tmp),
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.Y(Y[i])
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);
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end
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endgenerate
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(* techmap_simplemap *)
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module \$xnor ;
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endmodule
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// --------------------------------------------------------
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module \$reduce_and (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output [Y_WIDTH-1:0] Y;
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wire [A_WIDTH-1:0] buffer;
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genvar i;
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generate
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for (i = 1; i < A_WIDTH; i = i + 1) begin:V
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\$_AND_ gate (
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.A(A[i]),
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.B(buffer[i-1]),
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.Y(buffer[i])
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);
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end
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endgenerate
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assign buffer[0] = A[0];
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assign Y = buffer[A_WIDTH-1];
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(* techmap_simplemap *)
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module \$reduce_and ;
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endmodule
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// --------------------------------------------------------
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module \$reduce_or (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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output [Y_WIDTH-1:0] Y;
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wire [A_WIDTH-1:0] buffer;
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genvar i;
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generate
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for (i = 1; i < A_WIDTH; i = i + 1) begin:V
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\$_OR_ gate (
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.A(A[i]),
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.B(buffer[i-1]),
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.Y(buffer[i])
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);
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end
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endgenerate
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assign buffer[0] = A[0];
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assign Y = buffer[A_WIDTH-1];
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(* techmap_simplemap *)
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module \$reduce_or ;
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endmodule
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// --------------------------------------------------------
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module \$reduce_xor (A, Y);
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parameter A_SIGNED = 0;
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parameter A_WIDTH = 1;
|
||||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire [A_WIDTH-1:0] buffer;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 1; i < A_WIDTH; i = i + 1) begin:V
|
||||
\$_XOR_ gate (
|
||||
.A(A[i]),
|
||||
.B(buffer[i-1]),
|
||||
.Y(buffer[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign buffer[0] = A[0];
|
||||
assign Y = buffer[A_WIDTH-1];
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$reduce_xor ;
|
||||
endmodule
|
||||
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
module \$reduce_xnor (A, Y);
|
||||
|
||||
parameter A_SIGNED = 0;
|
||||
parameter A_WIDTH = 1;
|
||||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire [A_WIDTH-1:0] buffer;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 1; i < A_WIDTH; i = i + 1) begin:V
|
||||
\$_XOR_ gate (
|
||||
.A(A[i]),
|
||||
.B(buffer[i-1]),
|
||||
.Y(buffer[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign buffer[0] = A[0];
|
||||
\$_INV_ gate_inv (
|
||||
.A(buffer[A_WIDTH-1]),
|
||||
.Y(Y[0])
|
||||
);
|
||||
|
||||
generate
|
||||
if (Y_WIDTH > 1) begin:V
|
||||
assign Y[Y_WIDTH-1:1] = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$reduce_xnor ;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
module \$reduce_bool (A, Y);
|
||||
|
||||
parameter A_SIGNED = 0;
|
||||
parameter A_WIDTH = 1;
|
||||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire [A_WIDTH-1:0] buffer;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 1; i < A_WIDTH; i = i + 1) begin:V
|
||||
\$_OR_ gate (
|
||||
.A(A[i]),
|
||||
.B(buffer[i-1]),
|
||||
.Y(buffer[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign buffer[0] = A[0];
|
||||
assign Y = buffer[A_WIDTH-1];
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$reduce_bool ;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
|
@ -1181,157 +912,26 @@ endmodule
|
|||
// --------------------------------------------------------
|
||||
****/
|
||||
|
||||
module \$logic_not (A, Y);
|
||||
|
||||
parameter A_SIGNED = 0;
|
||||
parameter A_WIDTH = 1;
|
||||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire A_buf;
|
||||
|
||||
\$reduce_bool #(
|
||||
.A_SIGNED(A_SIGNED),
|
||||
.A_WIDTH(A_WIDTH),
|
||||
.Y_WIDTH(1)
|
||||
) A_logic (
|
||||
.A(A),
|
||||
.Y(A_buf)
|
||||
);
|
||||
|
||||
\$_INV_ gate (
|
||||
.A(A_buf),
|
||||
.Y(Y[0])
|
||||
);
|
||||
|
||||
generate
|
||||
if (Y_WIDTH > 1) begin:V
|
||||
assign Y[Y_WIDTH-1:1] = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$logic_not ;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
module \$logic_and (A, B, Y);
|
||||
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 1;
|
||||
parameter B_WIDTH = 1;
|
||||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
input [B_WIDTH-1:0] B;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire A_buf, B_buf;
|
||||
|
||||
\$reduce_bool #(
|
||||
.A_SIGNED(A_SIGNED),
|
||||
.A_WIDTH(A_WIDTH),
|
||||
.Y_WIDTH(1)
|
||||
) A_logic (
|
||||
.A(A),
|
||||
.Y(A_buf)
|
||||
);
|
||||
|
||||
\$reduce_bool #(
|
||||
.A_SIGNED(B_SIGNED),
|
||||
.A_WIDTH(B_WIDTH),
|
||||
.Y_WIDTH(1)
|
||||
) B_logic (
|
||||
.A(B),
|
||||
.Y(B_buf)
|
||||
);
|
||||
|
||||
\$_AND_ gate (
|
||||
.A(A_buf),
|
||||
.B(B_buf),
|
||||
.Y(Y[0])
|
||||
);
|
||||
|
||||
generate
|
||||
if (Y_WIDTH > 1) begin:V
|
||||
assign Y[Y_WIDTH-1:1] = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$logic_and ;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
module \$logic_or (A, B, Y);
|
||||
|
||||
parameter A_SIGNED = 0;
|
||||
parameter B_SIGNED = 0;
|
||||
parameter A_WIDTH = 1;
|
||||
parameter B_WIDTH = 1;
|
||||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
input [B_WIDTH-1:0] B;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire A_buf, B_buf;
|
||||
|
||||
\$reduce_bool #(
|
||||
.A_SIGNED(A_SIGNED),
|
||||
.A_WIDTH(A_WIDTH),
|
||||
.Y_WIDTH(1)
|
||||
) A_logic (
|
||||
.A(A),
|
||||
.Y(A_buf)
|
||||
);
|
||||
|
||||
\$reduce_bool #(
|
||||
.A_SIGNED(B_SIGNED),
|
||||
.A_WIDTH(B_WIDTH),
|
||||
.Y_WIDTH(1)
|
||||
) B_logic (
|
||||
.A(B),
|
||||
.Y(B_buf)
|
||||
);
|
||||
|
||||
\$_OR_ gate (
|
||||
.A(A_buf),
|
||||
.B(B_buf),
|
||||
.Y(Y[0])
|
||||
);
|
||||
|
||||
generate
|
||||
if (Y_WIDTH > 1) begin:V
|
||||
assign Y[Y_WIDTH-1:1] = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$logic_or ;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
module \$mux (A, B, S, Y);
|
||||
|
||||
parameter WIDTH = 1;
|
||||
|
||||
input [WIDTH-1:0] A, B;
|
||||
input S;
|
||||
output [WIDTH-1:0] Y;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_MUX_ gate (
|
||||
.A(A[i]),
|
||||
.B(B[i]),
|
||||
.S(S),
|
||||
.Y(Y[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$mux ;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
|
@ -1410,306 +1010,32 @@ endmodule
|
|||
|
||||
// --------------------------------------------------------
|
||||
|
||||
module \$sr (SET, CLR, Q);
|
||||
|
||||
parameter WIDTH = 0;
|
||||
parameter SET_POLARITY = 1'b1;
|
||||
parameter CLR_POLARITY = 1'b1;
|
||||
|
||||
input [WIDTH-1:0] SET, CLR;
|
||||
output reg [WIDTH-1:0] Q;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
if (SET_POLARITY == 0 && CLR_POLARITY == 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_SR_NN_ ff (
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
if (SET_POLARITY == 0 && CLR_POLARITY != 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_SR_NP_ ff (
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
if (SET_POLARITY != 0 && CLR_POLARITY == 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_SR_PN_ ff (
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
if (SET_POLARITY != 0 && CLR_POLARITY != 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_SR_PP_ ff (
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$sr ;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
module \$dff (CLK, D, Q);
|
||||
|
||||
parameter WIDTH = 1;
|
||||
parameter CLK_POLARITY = 1'b1;
|
||||
|
||||
input CLK;
|
||||
input [WIDTH-1:0] D;
|
||||
output [WIDTH-1:0] Q;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
if (CLK_POLARITY == 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DFF_N_ ff (
|
||||
.D(D[i]),
|
||||
.Q(Q[i]),
|
||||
.C(CLK)
|
||||
);
|
||||
end
|
||||
if (CLK_POLARITY != 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DFF_P_ ff (
|
||||
.D(D[i]),
|
||||
.Q(Q[i]),
|
||||
.C(CLK)
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$dff ;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
module \$adff (CLK, ARST, D, Q);
|
||||
|
||||
parameter WIDTH = 1;
|
||||
parameter CLK_POLARITY = 1'b1;
|
||||
parameter ARST_POLARITY = 1'b1;
|
||||
parameter ARST_VALUE = 0;
|
||||
|
||||
input CLK, ARST;
|
||||
input [WIDTH-1:0] D;
|
||||
output [WIDTH-1:0] Q;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
if (CLK_POLARITY == 0) begin:N
|
||||
if (ARST_POLARITY == 0) begin:NN
|
||||
if (ARST_VALUE[i] == 0) begin:NN0
|
||||
\$_DFF_NN0_ ff (
|
||||
.D(D[i]),
|
||||
.Q(Q[i]),
|
||||
.C(CLK),
|
||||
.R(ARST)
|
||||
);
|
||||
end else begin:NN1
|
||||
\$_DFF_NN1_ ff (
|
||||
.D(D[i]),
|
||||
.Q(Q[i]),
|
||||
.C(CLK),
|
||||
.R(ARST)
|
||||
);
|
||||
end
|
||||
end else begin:NP
|
||||
if (ARST_VALUE[i] == 0) begin:NP0
|
||||
\$_DFF_NP0_ ff (
|
||||
.D(D[i]),
|
||||
.Q(Q[i]),
|
||||
.C(CLK),
|
||||
.R(ARST)
|
||||
);
|
||||
end else begin:NP1
|
||||
\$_DFF_NP1_ ff (
|
||||
.D(D[i]),
|
||||
.Q(Q[i]),
|
||||
.C(CLK),
|
||||
.R(ARST)
|
||||
);
|
||||
end
|
||||
end
|
||||
end else begin:P
|
||||
if (ARST_POLARITY == 0) begin:PN
|
||||
if (ARST_VALUE[i] == 0) begin:PN0
|
||||
\$_DFF_PN0_ ff (
|
||||
.D(D[i]),
|
||||
.Q(Q[i]),
|
||||
.C(CLK),
|
||||
.R(ARST)
|
||||
);
|
||||
end else begin:PN1
|
||||
\$_DFF_PN1_ ff (
|
||||
.D(D[i]),
|
||||
.Q(Q[i]),
|
||||
.C(CLK),
|
||||
.R(ARST)
|
||||
);
|
||||
end
|
||||
end else begin:PP
|
||||
if (ARST_VALUE[i] == 0) begin:PP0
|
||||
\$_DFF_PP0_ ff (
|
||||
.D(D[i]),
|
||||
.Q(Q[i]),
|
||||
.C(CLK),
|
||||
.R(ARST)
|
||||
);
|
||||
end else begin:PP1
|
||||
\$_DFF_PP1_ ff (
|
||||
.D(D[i]),
|
||||
.Q(Q[i]),
|
||||
.C(CLK),
|
||||
.R(ARST)
|
||||
);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$adff ;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
module \$dffsr (CLK, SET, CLR, D, Q);
|
||||
|
||||
parameter WIDTH = 0;
|
||||
parameter CLK_POLARITY = 1'b1;
|
||||
parameter SET_POLARITY = 1'b1;
|
||||
parameter CLR_POLARITY = 1'b1;
|
||||
|
||||
input CLK;
|
||||
input [WIDTH-1:0] SET, CLR, D;
|
||||
output reg [WIDTH-1:0] Q;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
if (CLK_POLARITY == 0 && SET_POLARITY == 0 && CLR_POLARITY == 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DFFSR_NNN_ ff (
|
||||
.C(CLK),
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.D(D[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
if (CLK_POLARITY == 0 && SET_POLARITY == 0 && CLR_POLARITY != 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DFFSR_NNP_ ff (
|
||||
.C(CLK),
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.D(D[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
if (CLK_POLARITY == 0 && SET_POLARITY != 0 && CLR_POLARITY == 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DFFSR_NPN_ ff (
|
||||
.C(CLK),
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.D(D[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
if (CLK_POLARITY == 0 && SET_POLARITY != 0 && CLR_POLARITY != 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DFFSR_NPP_ ff (
|
||||
.C(CLK),
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.D(D[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
if (CLK_POLARITY != 0 && SET_POLARITY == 0 && CLR_POLARITY == 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DFFSR_PNN_ ff (
|
||||
.C(CLK),
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.D(D[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
if (CLK_POLARITY != 0 && SET_POLARITY == 0 && CLR_POLARITY != 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DFFSR_PNP_ ff (
|
||||
.C(CLK),
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.D(D[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
if (CLK_POLARITY != 0 && SET_POLARITY != 0 && CLR_POLARITY == 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DFFSR_PPN_ ff (
|
||||
.C(CLK),
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.D(D[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
if (CLK_POLARITY != 0 && SET_POLARITY != 0 && CLR_POLARITY != 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DFFSR_PPP_ ff (
|
||||
.C(CLK),
|
||||
.S(SET[i]),
|
||||
.R(CLR[i]),
|
||||
.D(D[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$dffsr ;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
module \$dlatch (EN, D, Q);
|
||||
|
||||
parameter WIDTH = 0;
|
||||
parameter EN_POLARITY = 1'b1;
|
||||
|
||||
input EN;
|
||||
input [WIDTH-1:0] D;
|
||||
output reg [WIDTH-1:0] Q;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
if (EN_POLARITY == 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DLATCH_N_ ff (
|
||||
.E(EN),
|
||||
.D(D[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
if (EN_POLARITY != 0)
|
||||
for (i = 0; i < WIDTH; i = i + 1) begin:V
|
||||
\$_DLATCH_P_ ff (
|
||||
.E(EN),
|
||||
.D(D[i]),
|
||||
.Q(Q[i])
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
(* techmap_simplemap *)
|
||||
module \$dlatch ;
|
||||
endmodule
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue