From 76dfa817904c5fa564234e020fe0898343a8523f Mon Sep 17 00:00:00 2001
From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Thu, 18 Jun 2020 17:42:36 +0000
Subject: [PATCH] cutpoint: Improve efficiency by iterating over module ports
 instead of module wires.

---
 passes/sat/cutpoint.cc | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc
index 26cc69211..27dc10523 100644
--- a/passes/sat/cutpoint.cc
+++ b/passes/sat/cutpoint.cc
@@ -126,15 +126,16 @@ struct CutpointPass : public Pass {
 				}
 
 				vector<Wire*> rewrite_wires;
-				for (auto wire : module->wires()) {
-					if (!wire->port_input)
-						continue;
-					int bit_count = 0;
-					for (auto &bit : sigmap(wire))
-						if (cutpoint_bits.count(bit))
-							bit_count++;
-					if (bit_count)
-						rewrite_wires.push_back(wire);
+				for (auto id : module->ports) {
+					RTLIL::Wire *wire = module->wire(id);
+					if (wire->port_input) {
+						int bit_count = 0;
+						for (auto &bit : sigmap(wire))
+							if (cutpoint_bits.count(bit))
+								bit_count++;
+						if (bit_count)
+							rewrite_wires.push_back(wire);
+					}
 				}
 
 				for (auto wire : rewrite_wires) {