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Fix: handle VCD variable references with and without whitespace

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Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
This commit is contained in:
Roland Coeurjoly 2024-09-30 14:08:35 +02:00
parent 1bf908dea8
commit 76c615b2ae
5 changed files with 88 additions and 1 deletions
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20
tests/sim/vector_assign.il Normal file
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# Generated by Yosys 0.45+139 (git sha1 e7fc1b0cc, g++ 13.2.0 -fPIC -O3)
autoidx 2
attribute \architecture "Behavioral"
attribute \library "work"
attribute \hdlname "vector_assign"
attribute \src "tests/verific/vector_assign.vhd:4.8-4.21"
module \vector_assign
attribute \src "tests/verific/vector_assign.vhd:6.9-6.10"
wire width 4 input 2 \a
attribute \src "tests/verific/vector_assign.vhd:7.9-7.10"
wire width 4 output 1 \b
attribute \src "tests/verific/vector_assign.vhd:13.5-13.6"
cell $pos $verific$buf_3$tests/verific/vector_assign.vhd:13$1
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \a
connect \Y \b
end
end