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Fix: handle VCD variable references with and without whitespace

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Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
This commit is contained in:
Roland Coeurjoly 2024-09-30 14:08:35 +02:00
parent 1bf908dea8
commit 76c615b2ae
5 changed files with 88 additions and 1 deletions
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28
tests/sim/var_reference_with_whitespace.vcd Normal file
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@ -0,0 +1,28 @@
$date
Fri Sep 27 11:58:46 2024
$end
$version
GHDL v0
$end
$timescale
1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module tb $end
$var reg 4 ! a [3:0] $end
$var reg 4 " b [3:0] $end
$scope module uut $end
$var reg 4 # a [3:0] $end
$var reg 4 $ b [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
b0001 !
b0001 "
b0001 #
b0001 $
#10000000