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Added equiv_make command
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e13a45ae61
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4 changed files with 260 additions and 1 deletions
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@ -1618,6 +1618,15 @@ RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a
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return cell;
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}
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RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
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{
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RTLIL::Cell *cell = addCell(name, "$equiv");
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cell->setPort("\\A", sig_a);
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cell->setPort("\\B", sig_b);
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cell->setPort("\\Y", sig_y);
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return cell;
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}
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RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity, bool clr_polarity)
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{
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RTLIL::Cell *cell = addCell(name, "$sr");
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