mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 14:13:23 +00:00
techmap, flatten: remove dead options.
After splitting the passes, some options can never be activated, and most conditions involving them become dead. Remove them, and also all of the newly dead code.
This commit is contained in:
whitequark
parent
6ac54a74fe
commit
76c4ee4ea5
2 changed files with 217 additions and 933 deletions
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@ -67,10 +67,6 @@ struct TechmapWorker
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pool<RTLIL::Module*> module_queue;
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dict<Module*, SigMap> sigmaps;
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pool<IdString> flatten_do_list;
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pool<IdString> flatten_done_list;
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pool<Cell*> flatten_keep_list;
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pool<string> log_msg_cache;
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struct TechmapWireData {
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@ -82,7 +78,6 @@ struct TechmapWorker
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bool extern_mode = false;
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bool assert_mode = false;
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bool flatten_mode = false;
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bool recursive_mode = false;
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bool autoproc_mode = false;
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bool ignore_wb = false;
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@ -168,13 +163,11 @@ struct TechmapWorker
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pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
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orig_cell_name = cell->name.str();
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if (!flatten_mode) {
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for (auto tpl_cell : tpl->cells())
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if (tpl_cell->name == ID::_TECHMAP_REPLACE_) {
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module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
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break;
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}
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}
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for (auto tpl_cell : tpl->cells())
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if (tpl_cell->name == ID::_TECHMAP_REPLACE_) {
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module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
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break;
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}
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dict<IdString, IdString> memory_renames;
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@ -205,7 +198,7 @@ struct TechmapWorker
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IdString posportname = stringf("$%d", tpl_w->port_id);
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positional_ports.emplace(posportname, tpl_w->name);
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if (!flatten_mode && tpl_w->get_bool_attribute(ID::techmap_autopurge) &&
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if (tpl_w->get_bool_attribute(ID::techmap_autopurge) &&
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(!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) &&
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(!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
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{
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@ -221,26 +214,16 @@ struct TechmapWorker
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apply_prefix(cell->name, w_name);
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RTLIL::Wire *w = module->wire(w_name);
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if (w != nullptr) {
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if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) {
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temp_renamed_wires[w] = w->name;
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module->rename(w, NEW_ID);
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w = nullptr;
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} else {
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w->attributes.erase(ID::hierconn);
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if (GetSize(w) < GetSize(tpl_w)) {
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log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
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log_id(tpl), log_id(tpl_w), log_id(module), log_id(cell));
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w->width = GetSize(tpl_w);
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}
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}
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temp_renamed_wires[w] = w->name;
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module->rename(w, NEW_ID);
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w = nullptr;
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}
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if (w == nullptr) {
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w = module->addWire(w_name, tpl_w);
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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if (!flatten_mode)
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w->attributes.erase(ID::techmap_autopurge);
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w->attributes.erase(ID::techmap_autopurge);
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if (tpl_w->get_bool_attribute(ID::_techmap_special_))
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w->attributes.clear();
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if (w->attributes.count(ID::src))
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@ -322,56 +305,37 @@ struct TechmapWorker
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log_assert(c.first.size() == c.second.size());
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if (flatten_mode)
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{
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// more conservative approach:
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// connect internal and external wires
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if (sigmaps.count(module) == 0)
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sigmaps[module].set(module);
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if (sigmaps.at(module)(c.first).has_const())
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log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
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log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
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// replace internal wires that are connected to external wires
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if (w->port_output && !w->port_input) {
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port_signal_map.add(c.second, c.first);
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} else
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if (!w->port_output && w->port_input) {
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port_signal_map.add(c.first, c.second);
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} else {
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module->connect(c);
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extra_connect = SigSig();
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}
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else
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{
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// approach that yields nicer outputs:
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// replace internal wires that are connected to external wires
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if (w->port_output && !w->port_input) {
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port_signal_map.add(c.second, c.first);
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} else
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if (!w->port_output && w->port_input) {
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port_signal_map.add(c.first, c.second);
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} else {
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module->connect(c);
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extra_connect = SigSig();
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}
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for (auto &attr : w->attributes) {
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if (attr.first == ID::src)
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continue;
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auto lhs = GetSize(extra_connect.first);
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auto rhs = GetSize(extra_connect.second);
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if (lhs > rhs)
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extra_connect.first.remove(rhs, lhs-rhs);
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else if (rhs > lhs)
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extra_connect.second.remove(lhs, rhs-lhs);
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module->connect(extra_connect);
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break;
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}
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for (auto &attr : w->attributes) {
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if (attr.first == ID::src)
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continue;
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auto lhs = GetSize(extra_connect.first);
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auto rhs = GetSize(extra_connect.second);
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if (lhs > rhs)
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extra_connect.first.remove(rhs, lhs-rhs);
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else if (rhs > lhs)
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extra_connect.second.remove(lhs, rhs-lhs);
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module->connect(extra_connect);
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break;
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}
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}
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for (auto tpl_cell : tpl->cells())
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{
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IdString c_name = tpl_cell->name;
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bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_);
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if (techmap_replace_cell)
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if (c_name == ID::_TECHMAP_REPLACE_)
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c_name = orig_cell_name;
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else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_."))
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c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
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@ -381,7 +345,7 @@ struct TechmapWorker
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RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
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design->select(module, c);
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if (!flatten_mode && c->type.begins_with("\\$"))
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if (c->type.begins_with("\\$"))
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c->type = c->type.substr(1);
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vector<IdString> autopurge_ports;
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@ -426,7 +390,7 @@ struct TechmapWorker
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if (c->attributes.count(ID::src))
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c->add_strpool_attribute(ID::src, extra_src_attrs);
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if (techmap_replace_cell)
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if (c_name == ID::_TECHMAP_REPLACE_)
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for (auto attr : cell->attributes)
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if (!c->attributes.count(attr.first))
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c->attributes[attr.first] = attr.second;
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@ -499,22 +463,6 @@ struct TechmapWorker
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continue;
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}
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if (flatten_mode) {
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bool keepit = cell->get_bool_attribute(ID::keep_hierarchy);
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for (auto &tpl_name : celltypeMap.at(cell_type))
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if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy))
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keepit = true;
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if (keepit) {
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if (!flatten_keep_list[cell]) {
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log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
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flatten_keep_list.insert(cell);
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}
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if (!flatten_done_list[cell->type])
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flatten_do_list.insert(cell->type);
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continue;
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}
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}
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for (auto &conn : cell->connections())
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{
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RTLIL::SigSpec sig = sigmap(conn.second);
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@ -564,172 +512,171 @@ struct TechmapWorker
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if (tpl->get_blackbox_attribute(ignore_wb))
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continue;
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if (!flatten_mode)
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std::string extmapper_name;
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if (tpl->get_bool_attribute(ID::techmap_simplemap))
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extmapper_name = "simplemap";
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if (tpl->get_bool_attribute(ID::techmap_maccmap))
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extmapper_name = "maccmap";
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if (tpl->attributes.count(ID::techmap_wrap))
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extmapper_name = "wrap";
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if (!extmapper_name.empty())
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{
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std::string extmapper_name;
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cell->type = cell_type;
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if (tpl->get_bool_attribute(ID::techmap_simplemap))
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extmapper_name = "simplemap";
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if (tpl->get_bool_attribute(ID::techmap_maccmap))
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extmapper_name = "maccmap";
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if (tpl->attributes.count(ID::techmap_wrap))
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extmapper_name = "wrap";
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if (!extmapper_name.empty())
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if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
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{
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cell->type = cell_type;
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std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
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if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
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for (auto &c : cell->parameters)
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m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
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if (extmapper_name == "wrap")
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m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
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RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
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RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
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if (extmapper_module == nullptr)
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{
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std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
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extmapper_module = extmapper_design->addModule(m_name);
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RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
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for (auto &c : cell->parameters)
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m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
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extmapper_cell->set_src_attribute(cell->get_src_attribute());
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if (extmapper_name == "wrap")
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m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
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RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
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RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
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if (extmapper_module == nullptr)
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{
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extmapper_module = extmapper_design->addModule(m_name);
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RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
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extmapper_cell->set_src_attribute(cell->get_src_attribute());
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int port_counter = 1;
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for (auto &c : extmapper_cell->connections_) {
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RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
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if (w->name.in(ID::Y, ID::Q))
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w->port_output = true;
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else
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w->port_input = true;
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w->port_id = port_counter++;
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c.second = w;
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}
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extmapper_module->fixup_ports();
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extmapper_module->check();
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if (extmapper_name == "simplemap") {
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log("Creating %s with simplemap.\n", log_id(extmapper_module));
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if (simplemap_mappers.count(extmapper_cell->type) == 0)
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log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
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simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
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extmapper_module->remove(extmapper_cell);
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}
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if (extmapper_name == "maccmap") {
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log("Creating %s with maccmap.\n", log_id(extmapper_module));
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if (extmapper_cell->type != ID($macc))
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log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
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maccmap(extmapper_module, extmapper_cell);
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extmapper_module->remove(extmapper_cell);
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}
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if (extmapper_name == "wrap") {
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std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
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log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
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mkdebug.on();
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Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
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log_continue = true;
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}
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int port_counter = 1;
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for (auto &c : extmapper_cell->connections_) {
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RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
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if (w->name.in(ID::Y, ID::Q))
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w->port_output = true;
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else
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w->port_input = true;
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w->port_id = port_counter++;
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c.second = w;
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}
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cell->type = extmapper_module->name;
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cell->parameters.clear();
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if (!extern_mode || in_recursion) {
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tpl = extmapper_module;
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goto use_wrapper_tpl;
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}
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auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
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if (!log_msg_cache.count(msg)) {
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log_msg_cache.insert(msg);
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log("%s\n", msg.c_str());
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}
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log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
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}
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else
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{
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auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
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if (!log_msg_cache.count(msg)) {
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log_msg_cache.insert(msg);
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log("%s\n", msg.c_str());
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}
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log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
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extmapper_module->fixup_ports();
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extmapper_module->check();
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if (extmapper_name == "simplemap") {
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if (simplemap_mappers.count(cell->type) == 0)
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log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type));
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simplemap_mappers.at(cell->type)(module, cell);
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log("Creating %s with simplemap.\n", log_id(extmapper_module));
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if (simplemap_mappers.count(extmapper_cell->type) == 0)
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log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
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simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
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extmapper_module->remove(extmapper_cell);
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}
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if (extmapper_name == "maccmap") {
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if (cell->type != ID($macc))
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log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
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maccmap(module, cell);
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log("Creating %s with maccmap.\n", log_id(extmapper_module));
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if (extmapper_cell->type != ID($macc))
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log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
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maccmap(extmapper_module, extmapper_cell);
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extmapper_module->remove(extmapper_cell);
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}
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module->remove(cell);
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cell = nullptr;
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if (extmapper_name == "wrap") {
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std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
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log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
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mkdebug.on();
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Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
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log_continue = true;
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}
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}
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did_something = true;
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mapped_cell = true;
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break;
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cell->type = extmapper_module->name;
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cell->parameters.clear();
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if (!extern_mode || in_recursion) {
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tpl = extmapper_module;
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goto use_wrapper_tpl;
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}
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auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
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if (!log_msg_cache.count(msg)) {
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log_msg_cache.insert(msg);
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log("%s\n", msg.c_str());
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}
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log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
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}
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else
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{
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auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
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if (!log_msg_cache.count(msg)) {
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log_msg_cache.insert(msg);
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log("%s\n", msg.c_str());
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}
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log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
|
||||
|
||||
if (extmapper_name == "simplemap") {
|
||||
if (simplemap_mappers.count(cell->type) == 0)
|
||||
log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type));
|
||||
simplemap_mappers.at(cell->type)(module, cell);
|
||||
}
|
||||
|
||||
if (extmapper_name == "maccmap") {
|
||||
if (cell->type != ID($macc))
|
||||
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
|
||||
maccmap(module, cell);
|
||||
}
|
||||
|
||||
module->remove(cell);
|
||||
cell = nullptr;
|
||||
}
|
||||
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (conn.first.begins_with("$"))
|
||||
continue;
|
||||
if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0)
|
||||
continue;
|
||||
if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
|
||||
goto next_tpl;
|
||||
parameters[conn.first] = conn.second.as_const();
|
||||
}
|
||||
did_something = true;
|
||||
mapped_cell = true;
|
||||
break;
|
||||
}
|
||||
|
||||
if (0) {
|
||||
next_tpl:
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (conn.first.begins_with("$"))
|
||||
continue;
|
||||
if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0)
|
||||
continue;
|
||||
if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
|
||||
goto next_tpl;
|
||||
parameters[conn.first] = conn.second.as_const();
|
||||
}
|
||||
|
||||
if (0) {
|
||||
next_tpl:
|
||||
continue;
|
||||
}
|
||||
|
||||
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
|
||||
parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type));
|
||||
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
|
||||
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
||||
for (auto &bit : v)
|
||||
bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
|
||||
}
|
||||
|
||||
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
|
||||
parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type));
|
||||
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
|
||||
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
||||
for (auto &bit : v)
|
||||
bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
|
||||
}
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) {
|
||||
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
||||
for (auto &bit : v)
|
||||
if (bit.wire != nullptr)
|
||||
bit = RTLIL::SigBit(RTLIL::State::Sx);
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
|
||||
}
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
|
||||
auto sig = sigmap(conn.second);
|
||||
RTLIL::Const value(State::Sx, sig.size());
|
||||
for (int i = 0; i < sig.size(); i++) {
|
||||
auto it = init_bits.find(sig[i]);
|
||||
if (it != init_bits.end()) {
|
||||
value[i] = it->second;
|
||||
}
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) {
|
||||
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
||||
for (auto &bit : v)
|
||||
if (bit.wire != nullptr)
|
||||
bit = RTLIL::SigBit(RTLIL::State::Sx);
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
|
||||
}
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
|
||||
auto sig = sigmap(conn.second);
|
||||
RTLIL::Const value(State::Sx, sig.size());
|
||||
for (int i = 0; i < sig.size(); i++) {
|
||||
auto it = init_bits.find(sig[i]);
|
||||
if (it != init_bits.end()) {
|
||||
value[i] = it->second;
|
||||
}
|
||||
parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value);
|
||||
}
|
||||
parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value);
|
||||
}
|
||||
}
|
||||
|
||||
{
|
||||
int unique_bit_id_counter = 0;
|
||||
dict<RTLIL::SigBit, int> unique_bit_id;
|
||||
unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
|
||||
|
|
@ -787,13 +734,9 @@ struct TechmapWorker
|
|||
}
|
||||
}
|
||||
|
||||
if (flatten_mode) {
|
||||
techmap_do_cache[tpl] = true;
|
||||
} else {
|
||||
RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
|
||||
if (constmapped_tpl != nullptr)
|
||||
tpl = constmapped_tpl;
|
||||
}
|
||||
RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
|
||||
if (constmapped_tpl != nullptr)
|
||||
tpl = constmapped_tpl;
|
||||
|
||||
if (techmap_do_cache.count(tpl) == 0)
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue