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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-11-03 13:38:04 -05:00 • committed by GitHub
commit 76c12f8f8c
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8 changed files with 77 additions and 11 deletions
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24
tests/techmap/dfflibmap_dff_not_next.lib Normal file
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@ -0,0 +1,24 @@
library (test_not_next) {
cell (dff_not_next) {
area: 1.0;
pin (QN) {
direction : output;
function : "STATE";
}
pin (CLK) {
direction : input;
clock : true;
}
pin (D) {
direction : input;
}
pin (RN) {
direction : input;
}
ff (STATE, STATEN) {
clocked_on: "CLK";
next_state: "!D";
preset : "!RN";
}
}
}

31
tests/techmap/dfflibmap_formal.ys
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@ -108,6 +108,37 @@ copy top top_unmapped
simplemap top
dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dffsr_not_next.lib top
async2sync
flatten
opt_clean -purge
equiv_make top top_unmapped equiv
equiv_induct equiv
equiv_status -assert equiv
##################################################################
design -reset
read_verilog <<EOT
module top(input C, D, R, output Q);
// DFF with preset
always @(posedge C or negedge R) begin
if (!R) Q <= 1'b1;
else Q <= D;
end
endmodule
EOT
proc
opt
read_liberty dfflibmap_dffn_dffe.lib
read_liberty dfflibmap_dff_not_next.lib
copy top top_unmapped
simplemap top
dfflibmap -liberty dfflibmap_dffn_dffe.lib -liberty dfflibmap_dff_not_next.lib top
async2sync
flatten
opt_clean -purge