mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

Add signed/unsigned tests

Browse source 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
This commit is contained in:
Kamil Rakoczy 2020-06-26 15:35:35 +02:00
parent 6f9be939bd
commit 76a34dc5f3
1 changed files with 28 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

28
tests/various/signed.ys Normal file
View file

@ -0,0 +1,28 @@
# SV LRM A2.2.1
read_verilog -sv <<EOT
module test_signed();
parameter integer signed a = 0;
parameter integer unsigned b = 0;
endmodule
EOT
design -reset
read_verilog -sv <<EOT
module test_signed();
parameter logic signed [7:0] a = 0;
parameter logic unsigned [7:0] b = 0;
endmodule
EOT
design -reset
logger -expect error "syntax error, unexpected TOK_INTEGER" 1
read_verilog -sv <<EOT
module test_signed();
parameter signed integer a = 0;
parameter unsigned integer b = 0;
endmodule
EOT