mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 14:13:23 +00:00
Code Activity

More bugfixes related to new RTLIL::IdString

Browse source
This commit is contained in:
Clifford Wolf 2014-08-02 16:03:18 +02:00
parent 08392aad8f
commit 768eb846c4
10 changed files with 60 additions and 44 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/techmap/techmap.cc
View file

@ -57,7 +57,7 @@ struct TechmapWorker
std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
std::map<RTLIL::Module*, bool> techmap_do_cache;
std::set<RTLIL::Module*> module_queue;
std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
struct TechmapWireData {
RTLIL::Wire *wire;
@ -479,7 +479,7 @@ struct TechmapWorker
cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
log("Analyzing pattern of constant bits for this cell:\n");
std::string new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
log_assert(map->module(new_tpl_name) == nullptr);
@ -824,7 +824,9 @@ struct TechmapPass : public Pass {
celltypeMap[it.first].insert(it.first);
}
worker.module_queue = design->modules();
for (auto module : design->modules())
worker.module_queue.insert(module);
while (!worker.module_queue.empty())
{
RTLIL::Module *module = *worker.module_queue.begin();