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More bugfixes related to new RTLIL::IdString
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parent
08392aad8f
commit
768eb846c4
10 changed files with 60 additions and 44 deletions
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@ -47,7 +47,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
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std::string id = RTLIL::escape_id(std::string(expr, id_len));
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if (!module->wires_.count(id))
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log_error("Can't resolve wire name %s.\n", RTLIL::id2cstr(id));
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log_error("Can't resolve wire name %s.\n", RTLIL::unescape_id(id).c_str());
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expr += id_len;
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return module->wires_.at(id);
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@ -234,7 +234,7 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
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}
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if (clk_sig.size() == 0 || data_sig.size() == 0)
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log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", RTLIL::id2cstr(module->name));
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log_error("FF cell %s has no next_state and/or clocked_on attribute.\n", log_id(module->name));
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for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
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{
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@ -311,7 +311,7 @@ static void create_latch(RTLIL::Module *module, LibertyAst *node)
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}
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if (enable_sig.size() == 0 || data_sig.size() == 0)
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log_error("Latch cell %s has no data_in and/or enable attribute.\n", RTLIL::id2cstr(module->name));
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log_error("Latch cell %s has no data_in and/or enable attribute.\n", log_id(module->name));
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for (bool rerun_invert_rollback = true; rerun_invert_rollback;)
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{
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@ -480,10 +480,10 @@ struct LibertyFrontend : public Frontend {
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if (design->has(cell_name)) {
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if (flag_ignore_redef)
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continue;
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log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
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log_error("Duplicate definition of cell/module %s.\n", RTLIL::unescape_id(cell_name).c_str());
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}
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// log("Processing cell type %s.\n", RTLIL::id2cstr(cell_name));
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// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str());
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RTLIL::Module *module = new RTLIL::Module;
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module->name = cell_name;
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@ -501,9 +501,9 @@ struct LibertyFrontend : public Frontend {
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{
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if (!flag_ignore_miss_dir)
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{
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log_error("Missing or invalid direction for pin %s of cell %s.\n", node->args.at(0).c_str(), RTLIL::id2cstr(module->name));
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log_error("Missing or invalid direction for pin %s of cell %s.\n", node->args.at(0).c_str(), log_id(module->name));
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} else {
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log("Ignoring cell %s with missing or invalid direction for pin %s.\n", RTLIL::id2cstr(module->name), node->args.at(0).c_str());
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log("Ignoring cell %s with missing or invalid direction for pin %s.\n", log_id(module->name), node->args.at(0).c_str());
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delete module;
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goto skip_cell;
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}
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@ -551,9 +551,9 @@ struct LibertyFrontend : public Frontend {
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{
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if (!flag_ignore_miss_func)
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{
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log_error("Missing function on output %s of cell %s.\n", RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name));
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log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
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} else {
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log("Ignoring cell %s with missing function on output %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
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delete module;
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goto skip_cell;
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}
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