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Add default entry to testcase

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This commit is contained in:
Eddie Hung 2019-04-11 15:03:40 -07:00
parent adc6efb584
commit 7685469ee2
1 changed files with 3 additions and 2 deletions
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5
tests/various/muxcover.ys
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@ -8,12 +8,13 @@ read_verilog -formal <<EOT
3'b?1?: Y = B; 3'b?1?: Y = B;
3'b1??: Y = C; 3'b1??: Y = C;
3'b000: Y = D; 3'b000: Y = D;
default: Y = 'bx;
endcase endcase
endmodule endmodule
EOT EOT
## Examle usage for "pmuxtree" and "muxcover" ## Example usage for "pmuxtree" and "muxcover"
proc proc
pmuxtree pmuxtree
@ -35,7 +36,7 @@ read_verilog -formal <<EOT
3'b010: Y = B; 3'b010: Y = B;
3'b100: Y = C; 3'b100: Y = C;
3'b000: Y = D; 3'b000: Y = D;
default: Y = 'bx; default: Y = 'bx;
endcase endcase
endmodule endmodule
EOT EOT