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mirror of https://github.com/YosysHQ/yosys synced 2026-05-24 19:06:22 +00:00
This commit is contained in:
Miodrag Milanovic 2026-03-26 08:14:16 +01:00
parent bfd3e150fa
commit 76732497b9
8 changed files with 75 additions and 76 deletions

View file

@ -5,16 +5,13 @@ sys.path.append("..")
import gen_tests_makefile
def cmd(lines):
return " && \\\n".join(lines)
def initial_display():
gen_tests_makefile.generate_target("initial_display", cmd([
gen_tests_makefile.generate_cmd_test("initial_display", [
f"$(YOSYS) -p \"read_verilog initial_display.v\" | awk '/<<<BEGIN>>>/,/<<<END>>>/ {{print $$0}}' >yosys-initial_display.log 2>&1",
"iverilog -o iverilog-initial_display initial_display.v",
"./iverilog-initial_display >iverilog-initial_display.log",
"diff yosys-initial_display.log iverilog-initial_display.log",
]))
])
def always_display():
@ -28,11 +25,11 @@ def always_display():
]
for name, defs in cases:
gen_tests_makefile.generate_target(f"always_display_{name}", cmd([
gen_tests_makefile.generate_cmd_test(f"always_display_{name}", [
f"$(YOSYS) -p \"read_verilog {defs} always_display.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-1.v",
f"$(YOSYS) -p \"read_verilog yosys-always_display-{name}-1.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-2.v",
f"diff yosys-always_display-{name}-1.v yosys-always_display-{name}-2.v",
]))
])
def roundtrip():
@ -48,7 +45,7 @@ def roundtrip():
]
for name, defs in cases:
gen_tests_makefile.generate_target(f"roundtrip_{name}", cmd([
gen_tests_makefile.generate_cmd_test(f"roundtrip_{name}", [
f"$(YOSYS) -p \"read_verilog {defs} roundtrip.v; proc; clean\" -o yosys-roundtrip-{name}-1.v",
f"$(YOSYS) -p \"read_verilog yosys-roundtrip-{name}-1.v; proc; clean\" -o yosys-roundtrip-{name}-2.v",
f"diff yosys-roundtrip-{name}-1.v yosys-roundtrip-{name}-2.v",
@ -64,14 +61,14 @@ def roundtrip():
f"diff iverilog-roundtrip-{name}.log iverilog-roundtrip-{name}-1.log",
f"diff iverilog-roundtrip-{name}-1.log iverilog-roundtrip-{name}-2.log",
]))
])
def cxxrtl():
cases = ["always_full", "always_comb"]
for name in cases:
gen_tests_makefile.generate_target(f"cxxrtl_{name}", cmd([
gen_tests_makefile.generate_cmd_test(f"cxxrtl_{name}", [
f"$(YOSYS) -p \"read_verilog {name}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-{name}.cc\"",
f"$${{CXX:-g++}} -std=c++11 -o yosys-{name} -I../../backends/cxxrtl/runtime {name}_tb.cc -lstdc++",
f"./yosys-{name} 2>yosys-{name}.log",
@ -80,19 +77,19 @@ def cxxrtl():
f"./iverilog-{name} | grep -v \"$finish called\" >iverilog-{name}.log",
f"diff iverilog-{name}.log yosys-{name}.log",
]))
])
def extra():
gen_tests_makefile.generate_target("always_full_equiv", cmd([
gen_tests_makefile.generate_cmd_test("always_full_equiv", [
"$(YOSYS) -p \"read_verilog always_full.v; prep; clean\" -o yosys-always_full-1.v",
"iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v",
"./iverilog-always_full-1 > tmp.log",
"grep -v '\\$finish called' tmp.log > iverilog-always_full-1.log",
"diff iverilog-always_full.log iverilog-always_full-1.log",
]), deps=["cxxrtl_always_full"])
], deps=["cxxrtl_always_full"])
gen_tests_makefile.generate_target("display_lm", cmd([
gen_tests_makefile.generate_cmd_test("display_lm", [
"$(YOSYS) -p \"read_verilog display_lm.v\" >yosys-display_lm.log 2>&1",
"$(YOSYS) -p \"read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc\"",
f"$${{CXX:-g++}} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++",
@ -101,7 +98,7 @@ def extra():
"grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm.log\"",
"grep \"^%l: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\"",
"grep \"^%m: \\\\\\bot\\$$\" \"yosys-display_lm_cc.log\"",
]))
])
def main():