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opt_clean: Better memory handling.

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Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself).  With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.
This commit is contained in:
Marcelina Kościelnicka 2020-10-08 13:33:47 +02:00
parent fd306b0520
commit 7670a89e1f
2 changed files with 94 additions and 8 deletions
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49
tests/opt/opt_clean_mem.ys Normal file
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read_verilog <<EOT
module top(...);
input [7:0] wa;
input [7:0] ra1;
input [7:0] ra2;
input [7:0] wd;
input clk;
wire [7:0] rd1;
wire [7:0] rd2;
reg [7:0] mem[0:7];
always @(posedge clk)
mem[wa] <= wd;
assign rd1 = mem[ra1];
assign rd2 = mem[ra2];
initial mem[8'h12] = 8'h34;
endmodule
EOT
proc
memory_dff
select -assert-count 2 t:$memrd
select -assert-count 1 t:$memwr
select -assert-count 1 t:$meminit
design -save orig
opt_clean
select -assert-none t:$memrd
select -assert-none t:$memwr
select -assert-none t:$meminit
design -load orig
expose top/rd1
opt_clean
select -assert-count 1 t:$memrd
select -assert-count 1 t:$memwr
select -assert-count 1 t:$meminit
design -load orig
expose top/rd1 top/rd2
opt_clean
select -assert-count 2 t:$memrd
select -assert-count 1 t:$memwr
select -assert-count 1 t:$meminit