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read_aiger: make $and/$not/$lut the prefix not suffix

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This commit is contained in:
Eddie Hung 2020-01-13 17:34:37 -08:00
parent ca2f3db53f
commit 766e16b525
2 changed files with 9 additions and 9 deletions
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10
frontends/aiger/aigerparse.cc
View file

@ -346,7 +346,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
} }
log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
module->addNotGate(stringf("$%d$not", variable), wire_inv, wire); module->addNotGate(stringf("$not$%d", variable), wire_inv, wire);
return wire; return wire;
} }
@ -445,10 +445,10 @@ void AigerReader::parse_xaiger()
log_assert(o.wire == nullptr); log_assert(o.wire == nullptr);
lut_mask[gray] = o.data; lut_mask[gray] = o.data;
} }
RTLIL::Cell *output_cell = module->cell(stringf("$%d$and", rootNodeID)); RTLIL::Cell *output_cell = module->cell(stringf("$and$%d", rootNodeID));
log_assert(output_cell); log_assert(output_cell);
module->remove(output_cell); module->remove(output_cell);
module->addLut(stringf("$%d$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask)); module->addLut(stringf("$lut$%d", rootNodeID), input_sig, output_sig, std::move(lut_mask));
} }
} }
else if (c == 'r') { else if (c == 'r') {
@ -620,7 +620,7 @@ void AigerReader::parse_aiger_ascii()
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire); module->addAndGate("$and" + o_wire->name.str(), i1_wire, i2_wire, o_wire);
} }
std::getline(f, line); // Ignore up to start of next line std::getline(f, line); // Ignore up to start of next line
} }
@ -746,7 +746,7 @@ void AigerReader::parse_aiger_binary()
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire); module->addAndGate("$and" + o_wire->name.str(), i1_wire, i2_wire, o_wire);
} }
} }

8
passes/techmap/abc9.cc
View file

@ -348,7 +348,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
log_assert(!design->module(ID($__abc9__))); log_assert(!design->module(ID($__abc9__)));
{ {
AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, /*buffer.c_str()*/ "" /* map_filename */, true /* wideports */); AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
reader.parse_xaiger(); reader.parse_xaiger();
} }
ifs.close(); ifs.close();
@ -472,16 +472,16 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
// (TODO: Optimise by not cloning unless will increase depth) // (TODO: Optimise by not cloning unless will increase depth)
RTLIL::IdString driver_name; RTLIL::IdString driver_name;
if (GetSize(a_bit.wire) == 1) if (GetSize(a_bit.wire) == 1)
driver_name = stringf("%s$lut", a_bit.wire->name.c_str()); driver_name = stringf("$lut%s", a_bit.wire->name.c_str());
else else
driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset); driver_name = stringf("$lut%s[%d]", a_bit.wire->name.c_str(), a_bit.offset);
driver_lut = mapped_mod->cell(driver_name); driver_lut = mapped_mod->cell(driver_name);
} }
if (!driver_lut) { if (!driver_lut) {
// If a driver couldn't be found (could be from PI or box CI) // If a driver couldn't be found (could be from PI or box CI)
// then implement using a LUT // then implement using a LUT
cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())), cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())),
RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset), RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset), RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01")); RTLIL::Const::from_string("01"));