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Bugfix in fsm_extract
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f0c9a099d2
commit
766dd51447
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@ -56,6 +56,17 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
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std::set<sig2driver_entry_t> cellport_list;
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std::set<sig2driver_entry_t> cellport_list;
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sig2driver.find(sig, cellport_list);
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sig2driver.find(sig, cellport_list);
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if (GetSize(cellport_list) > 1) {
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log(" found %d combined drivers for state signal %s.\n", GetSize(cellport_list), log_signal(sig));
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return false;
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}
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if (GetSize(cellport_list) < 1) {
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log(" found no driver for state signal %s.\n", log_signal(sig));
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return false;
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}
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for (auto &cellport : cellport_list)
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for (auto &cellport : cellport_list)
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{
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{
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RTLIL::Cell *cell = module->cells_.at(cellport.first);
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RTLIL::Cell *cell = module->cells_.at(cellport.first);
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@ -90,9 +101,11 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
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log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state));
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log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state));
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} while (0);
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} while (0);
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if (ctrl.extract(sig_s).size() == 0) {
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for (auto sig_s_bit : sig_s) {
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log(" found ctrl input: %s\n", log_signal(sig_s));
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if (ctrl.extract(sig_s_bit).empty()) {
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ctrl.append(sig_s);
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log(" found ctrl input: %s\n", log_signal(sig_s_bit));
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ctrl.append(sig_s_bit);
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}
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}
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}
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if (!find_states(sig_aa, dff_out, ctrl, states))
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if (!find_states(sig_aa, dff_out, ctrl, states))
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