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Changes to "memory" pass for new $memwr/$mem WR_EN interface

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This commit is contained in:
Clifford Wolf 2014-07-16 12:13:13 +02:00
parent dcdd5c11b4
commit 765f172211
3 changed files with 56 additions and 38 deletions
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2
passes/memory/memory_unpack.cc
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@ -74,7 +74,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
cell->parameters["\\PRIORITY"] = i;
cell->connections["\\CLK"] = memory->connections.at("\\WR_CLK").extract(i, 1);
cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i, 1);
cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i*mem->width, mem->width);
cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits);
cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width);
module->add(cell);