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Changes to "memory" pass for new $memwr/$mem WR_EN interface

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This commit is contained in:
Clifford Wolf 2014-07-16 12:13:13 +02:00
parent dcdd5c11b4
commit 765f172211
3 changed files with 56 additions and 38 deletions
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4
passes/memory/memory_collect.cc
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@ -88,7 +88,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
clk_polarity.extend(1, false);
addr.extend(addr_bits, false);
data.extend(memory->width, false);
en.extend(1, false);
en.extend(memory->width, false);
sig_wr_clk.append(clk);
sig_wr_clk_enable.append(clk_enable);
@ -147,7 +147,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
assert(sig_wr_clk_polarity.width == wr_ports && sig_wr_clk_polarity.is_fully_const());
assert(sig_wr_addr.width == wr_ports * addr_bits);
assert(sig_wr_data.width == wr_ports * memory->width);
assert(sig_wr_en.width == wr_ports);
assert(sig_wr_en.width == wr_ports * memory->width);
mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0);