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https://github.com/YosysHQ/yosys
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patch: split into single-output patch + multi-output patch_ports; drop input-cone gc
This commit is contained in:
Emil J. Tywoniak
parent
61b0dfd3bf
commit
7656347b44
7 changed files with 220 additions and 256 deletions
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@ -54,7 +54,6 @@ struct RTLIL::SigNormIndex
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module->fixup_ports();
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setup_module_inputs();
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setup_driven_wires();
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setup_module_outputs_and_publics();
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setup_fanout();
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}
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@ -111,72 +110,6 @@ struct RTLIL::SigNormIndex
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}
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}
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// Creates $output_port cells consuming each pure-output module port wire
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// and $public cells consuming each public-named wire that isn't already
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// covered by an $input_port or $output_port. These act as fanout sentinels
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// so local GC (e.g. in Patch) won't remove driver cells whose only purpose
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// is to feed a port or a user-visible wire.
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void setup_module_outputs_and_publics() {
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std::vector<Cell *> cells_to_remove;
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dict<Wire *, Cell *> output_port_cells;
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dict<Wire *, Cell *> public_cells;
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for (auto cell : module->cells()) {
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if (cell->type != ID($output_port) && cell->type != ID($public))
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continue;
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auto const &sig_a = cell->getPort(ID::A);
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Wire *wire = nullptr;
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if (!sig_a.is_wire()) {
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cells_to_remove.push_back(cell);
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continue;
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}
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wire = sig_a.as_wire();
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if (cell->type == ID($output_port)) {
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if (wire->port_output && !wire->port_input && !output_port_cells.count(wire))
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output_port_cells.emplace(wire, cell);
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else
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cells_to_remove.push_back(cell);
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} else { // $public
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bool is_pure_input = wire->port_input && !wire->port_output;
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bool is_pure_output = wire->port_output && !wire->port_input;
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if (wire->name.isPublic() && !is_pure_input && !is_pure_output && !public_cells.count(wire))
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public_cells.emplace(wire, cell);
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else
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cells_to_remove.push_back(cell);
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}
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}
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for (auto cell : cells_to_remove)
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module->remove(cell);
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for (auto portname : module->ports) {
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Wire *wire = module->wire(portname);
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if (wire->port_output && !wire->port_input && !output_port_cells.count(wire)) {
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Cell *cell = module->addCell(NEW_ID, ID($output_port));
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cell->setParam(ID::WIDTH, GetSize(wire));
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cell->setPort(ID::A, wire);
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output_port_cells.emplace(wire, cell);
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}
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}
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for (auto &it : module->wires_) {
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Wire *wire = it.second;
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if (!wire->name.isPublic())
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continue;
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bool is_pure_input = wire->port_input && !wire->port_output;
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bool is_pure_output = wire->port_output && !wire->port_input;
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if (is_pure_input || is_pure_output)
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continue;
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if (public_cells.count(wire))
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continue;
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Cell *cell = module->addCell(NEW_ID, ID($public));
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cell->setParam(ID::WIDTH, GetSize(wire));
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cell->setPort(ID::A, wire);
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public_cells.emplace(wire, cell);
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}
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}
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void setup_driven_wires() {
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for (auto cell : module->cells()) {
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xlog("setup_driven_wires cell %s %s\n", cell->type, cell->name);
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@ -421,7 +354,7 @@ void RTLIL::Design::sigNormalize(bool enable)
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// TODO inefficient?
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std::vector<Cell*> cells_snapshot = module->cells();
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for (auto cell : cells_snapshot) {
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if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
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if (cell->type == ID($input_port))
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module->remove(cell);
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}
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}
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@ -1,6 +1,7 @@
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#include "kernel/unstable/patch.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include "kernel/newcelltypes.h"
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#include "kernel/rtlil.h"
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YOSYS_NAMESPACE_BEGIN
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@ -45,56 +46,6 @@ RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *othe
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return wire;
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}
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void Patch::gc(Cell* old_cell, bool track, pool<string>* src_pool) {
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log_debug("gc %s\n", old_cell->name);
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if (old_cell->type.in(ID($input_port), ID($output_port), ID($public)))
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return;
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pool<Cell*> inputs;
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for (auto [port_name, sig] : old_cell->connections()) {
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auto dir = old_cell->port_dir(port_name);
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// Unknown port direction (e.g. user module instance whose interface
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// isn't registered): can't decide input vs output, so don't gc it.
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// TODO: should be log_assert once PD_UNKNOWN is fixed at the source
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// (see claude-notes.md).
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if (dir == PD_UNKNOWN)
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return;
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// TODO only running GC through whole connections?
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log_debug("\tport %s\n", port_name);
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if (sig.size() && sig.is_wire()) {
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if (dir == PD_OUTPUT || dir == PD_INOUT) {
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for (auto bit : sig) {
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// Reject GC if used
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if (!mod->fanout(bit).empty()) {
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log_debug("\treject fanout\n");
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return;
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} else
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log_debug("\tok\n");
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}
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}
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if (dir == PD_INPUT || dir == PD_INOUT) {
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Wire* in_wire = sig.as_wire();
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log_assert(in_wire);
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log_debug("\twire %s\n", in_wire->name);
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if (in_wire->known_driver() && !leaves.count(in_wire))
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inputs.insert(in_wire->driverCell());
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}
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}
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}
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log_debug("\tremove %s\n", old_cell->name);
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// Only track recursively-removed cells. The top-level patched cell is the
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// caller's current iteration variable and won't be re-encountered.
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if (track && removed_cells)
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removed_cells->insert(old_cell);
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// The cell about to be removed contributes its src so all the cells gc'd
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// in this patch (top-level + input cone) get merged into the new cells'
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// src — that's the "transfer src automatically" guarantee.
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if (src_pool)
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src_pool->insert(old_cell->get_src_attribute());
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old_cell->module->remove(old_cell);
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for (auto input : inputs)
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gc(input, /*track=*/true, src_pool);
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}
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Wire* Patch::commit_wire(std::unique_ptr<Wire> wire) {
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Wire* raw = wire.release();
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mod->wires_[raw->name] = raw;
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@ -110,63 +61,142 @@ Cell* Patch::commit_cell(std::unique_ptr<Cell> cell) {
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return raw;
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}
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void Patch::patch(Cell* old_cell, IdString old_port, SigSpec new_sig) {
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patch(old_cell, {{old_port, new_sig}}, nullptr);
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std::vector<Cell*> Patch::commit_staged() {
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std::vector<Cell*> committed;
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committed.reserve(cells_.size());
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for (auto& cell : cells_) {
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cell->fixup_parameters();
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committed.push_back(commit_cell(std::move(cell)));
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}
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for (auto& wire : wires_)
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commit_wire(std::move(wire));
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cells_.clear();
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wires_.clear();
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return committed;
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}
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void Patch::patch(Cell* old_cell, const std::vector<std::pair<IdString, SigSpec>> &port_replacements) {
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patch(old_cell, port_replacements, nullptr);
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}
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void Patch::patch(Cell* old_cell, IdString old_port, SigSpec new_sig, Cell* merge_src_into) {
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patch(old_cell, {{old_port, new_sig}}, merge_src_into);
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}
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void Patch::patch(Cell* old_cell, const std::vector<std::pair<IdString, SigSpec>> &port_replacements, Cell* merge_src_into) {
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std::vector<SigSpec> old_sigs;
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for (auto &[port, new_sig] : port_replacements) {
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SigSpec old_sig = old_cell->getPort(port);
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if (old_sig.size() != new_sig.size())
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log_error("patch size mismatch on cell %s port %s: old %d (%s) vs new %d (%s)\n",
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log_id(old_cell->name), log_id(port), old_sig.size(), log_signal(old_sig),
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new_sig.size(), log_signal(new_sig));
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log_debug("patching %s %s which is %s with %s:\n", old_cell->name, port, log_signal(old_sig), log_signal(new_sig));
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old_sigs.push_back(old_sig);
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namespace {
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void collect_src(Cell* root, const std::vector<Cell*>& extras,
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Cell* merge_src_into, pool<std::string>& out)
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{
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out.insert(root->get_src_attribute());
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for (Cell* c : extras)
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if (c)
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out.insert(c->get_src_attribute());
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if (merge_src_into)
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out.insert(merge_src_into->get_src_attribute());
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}
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// Record leaves (existing wires consumed as inputs by the new cells) so
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// gc() stops at them. Detected via bit.wire->module being non-null:
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// uncommitted wires belong to no module yet.
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for (auto& cell : cells_) {
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for (auto& [port_name, sig] : cell->connections()) {
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auto dir = cell->port_dir(port_name);
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if (dir == PD_INPUT || dir == PD_INOUT) {
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for (auto bit : sig) {
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if (bit.is_wire() && bit.wire->module)
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leaves.insert(bit.wire);
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}
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void apply_src(const pool<std::string>& src_pool,
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const std::vector<Cell*>& targets, Cell* merge_src_into)
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{
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std::string src_str = AttrObject::strpool_attribute_to_str(src_pool);
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for (Cell* c : targets)
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c->set_src_attribute(src_str);
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if (merge_src_into)
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merge_src_into->set_src_attribute(src_str);
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}
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// Verifies via newcelltypes that root_cell has exactly one output port
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// and that it matches `expected_port`.
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void assert_single_output(Cell* root_cell, IdString expected_port) {
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int count = 0;
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IdString found;
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for (auto &[port, sig] : root_cell->connections()) {
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if (root_cell->output(port)) {
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found = port;
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count++;
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}
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}
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if (count != 1)
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log_error("Patch: cell %s of type %s has %d output ports, expected exactly one\n",
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log_id(root_cell->name), log_id(root_cell->type), count);
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if (found != expected_port)
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log_error("Patch: cell %s of type %s sole output port %s does not match patched port %s\n",
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log_id(root_cell->name), log_id(root_cell->type),
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log_id(found), log_id(expected_port));
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}
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}
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// Commit new cells/wires first so new_sig becomes a driven signal in the
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// signorm index before we merge. Track raw pointers so we can update
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// their src attribute after gc finishes collecting from removed cells.
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std::vector<Cell*> committed_new_cells;
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committed_new_cells.reserve(cells_.size());
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for (auto& cell: cells_) {
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cell->fixup_parameters();
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committed_new_cells.push_back(commit_cell(std::move(cell)));
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void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig,
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const std::vector<Cell*>& extras, Cell* merge_src_into)
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{
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assert_single_output(root_cell, old_port);
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SigSpec old_sig = root_cell->getPort(old_port);
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if (old_sig.size() != new_sig.size())
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log_error("patch size mismatch on cell %s port %s: old %d (%s) vs new %d (%s)\n",
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log_id(root_cell->name), log_id(old_port),
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old_sig.size(), log_signal(old_sig),
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new_sig.size(), log_signal(new_sig));
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log_debug("patching %s %s which is %s with %s\n",
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log_id(root_cell->name), log_id(old_port),
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log_signal(old_sig), log_signal(new_sig));
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pool<std::string> src_pool;
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collect_src(root_cell, extras, merge_src_into, src_pool);
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std::vector<Cell*> committed = commit_staged();
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apply_src(src_pool, committed, merge_src_into);
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// Drop root_cell's driver on the output port BEFORE wiring old_sig to
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// new_sig — otherwise old_sig would briefly have two drivers (root_cell
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// and new_sig) which signorm flags as conflicting.
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root_cell->unsetPort(old_port);
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if (map)
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map->add(old_sig, new_sig);
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mod->connect_incremental(old_sig, new_sig);
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// Remove root cell only — no input-cone walk.
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mod->remove(root_cell);
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}
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void Patch::patch_ports(Cell* root_cell,
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const std::vector<std::pair<IdString, SigSpec>>& port_replacements,
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const std::vector<Cell*>& extras, Cell* merge_src_into)
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{
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// Verify each listed port is an output of root_cell and that the
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// replacements cover every output port of root_cell.
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pool<IdString> listed;
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std::vector<SigSpec> old_sigs;
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old_sigs.reserve(port_replacements.size());
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for (auto &[port, new_sig] : port_replacements) {
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if (!root_cell->output(port))
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log_error("patch_ports: cell %s of type %s port %s is not an output\n",
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log_id(root_cell->name), log_id(root_cell->type), log_id(port));
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SigSpec old_sig = root_cell->getPort(port);
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if (old_sig.size() != new_sig.size())
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log_error("patch_ports size mismatch on cell %s port %s: old %d (%s) vs new %d (%s)\n",
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log_id(root_cell->name), log_id(port),
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old_sig.size(), log_signal(old_sig),
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new_sig.size(), log_signal(new_sig));
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listed.insert(port);
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old_sigs.push_back(old_sig);
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}
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for (auto &[port, sig] : root_cell->connections())
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if (root_cell->output(port) && !listed.count(port))
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log_error("patch_ports: cell %s of type %s has output port %s not in port_replacements\n",
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log_id(root_cell->name), log_id(root_cell->type), log_id(port));
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for (auto& wire: wires_)
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commit_wire(std::move(wire));
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pool<std::string> src_pool;
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collect_src(root_cell, extras, merge_src_into, src_pool);
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std::vector<Cell*> committed = commit_staged();
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apply_src(src_pool, committed, merge_src_into);
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// Drop every port (inputs included) so root_cell becomes a disconnected
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// shell before we wire old_sigs to new_sigs. Doing this first ensures
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// the old port signals are not briefly double-driven by root_cell and
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// the new connection.
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std::vector<IdString> all_ports;
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all_ports.reserve(root_cell->connections().size());
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for (auto &[port, sig] : root_cell->connections())
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all_ports.push_back(port);
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for (auto port : all_ports)
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root_cell->unsetPort(port);
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log_assert(root_cell->connections().empty());
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// Now drop old_cell's drivers so old_sigs are undriven, then merge each
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// into its new_sig. connect_incremental updates sigmap and re-normalizes
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// fanout consumers in place — no full sigNormalize needed.
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for (auto &[port, new_sig] : port_replacements)
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old_cell->setPort(port, SigSpec());
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for (size_t i = 0; i < port_replacements.size(); i++) {
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auto &[port, new_sig] = port_replacements[i];
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if (map)
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@ -174,24 +204,7 @@ void Patch::patch(Cell* old_cell, const std::vector<std::pair<IdString, SigSpec>
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mod->connect_incremental(old_sigs[i], new_sig);
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}
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// gc removes old_cell AND any newly-dead input-cone cells, contributing
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// each removed cell's src into the pool. The merged-into cell (e.g. an
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// opt_merge keep_cell) and any caller-bequeathed pool entries also get
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// folded in here.
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pool<string> src_pool;
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if (merge_src_into)
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src_pool.insert(merge_src_into->get_src_attribute());
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gc(old_cell, /*track=*/false, &src_pool);
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std::string src_str = AttrObject::strpool_attribute_to_str(src_pool);
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for (Cell* c : committed_new_cells)
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c->set_src_attribute(src_str);
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if (merge_src_into)
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merge_src_into->set_src_attribute(src_str);
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cells_.clear();
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wires_.clear();
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leaves.clear();
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mod->remove(root_cell);
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}
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void Patch::commit_inheriting_src(Cell* src_source) {
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@ -207,4 +220,4 @@ void Patch::commit_inheriting_src(Cell* src_source) {
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wires_.clear();
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}
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YOSYS_NAMESPACE_END
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YOSYS_NAMESPACE_END
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@ -9,9 +9,6 @@ YOSYS_NAMESPACE_BEGIN
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// No virtual methods — subclasses cannot be dispatched through a Patch pointer.
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struct RTLIL::Patch : public CellAdderMixin<RTLIL::Patch>
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{
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private:
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void gc(Cell* old_cell, bool track = false, pool<std::string>* src_pool = nullptr);
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protected:
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void add(RTLIL::Wire *wire);
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void add(RTLIL::Cell *cell);
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@ -20,12 +17,13 @@ protected:
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Cell* commit_cell(std::unique_ptr<Cell> cell);
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Wire* commit_wire(std::unique_ptr<Wire> wire);
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pool<Wire*> leaves = {};
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// Move staged cells_/wires_ into the module. Returns raw pointers to
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// the committed new cells in insertion order.
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std::vector<Cell*> commit_staged();
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public:
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Module* mod;
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SigMap* map;
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pool<Cell*>* removed_cells = nullptr;
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vector<std::unique_ptr<Wire>> wires_ = {};
|
||||
vector<std::unique_ptr<Cell>> cells_ = {};
|
||||
|
||||
|
|
@ -33,22 +31,36 @@ public:
|
|||
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
|
||||
const std::vector<RTLIL::SigSig> &connections() const;
|
||||
|
||||
void patch(Cell* old_cell, IdString old_port, SigSpec new_sig);
|
||||
void patch(Cell* old_cell, const std::vector<std::pair<IdString, SigSpec>> &port_replacements);
|
||||
// Compatible rewrite: root_cell's type has exactly one output port
|
||||
// (asserted via kernel/newcelltypes.h). Rewires that output's signal to
|
||||
// new_sig, auto-merges src from root_cell + each cell in `extras` (and
|
||||
// merge_src_into if set) into every staged new cell and into
|
||||
// merge_src_into, then removes root_cell from the module. No input-cone
|
||||
// walk: only root_cell is removed.
|
||||
void patch(Cell* root_cell, IdString old_port, SigSpec new_sig,
|
||||
const std::vector<Cell*>& extras = {},
|
||||
Cell* merge_src_into = nullptr);
|
||||
|
||||
// Variants for "merge old_cell into an existing keep_cell" (e.g.
|
||||
// opt_merge): the old_cell's src attribute is collected and combined
|
||||
// with merge_src_into's existing src, and the result is set on
|
||||
// merge_src_into. Any new cells in cells_ also receive the combined src.
|
||||
void patch(Cell* old_cell, IdString old_port, SigSpec new_sig, Cell* merge_src_into);
|
||||
void patch(Cell* old_cell, const std::vector<std::pair<IdString, SigSpec>> &port_replacements, Cell* merge_src_into);
|
||||
// Multi-output rewrite: transfer a list of output ports to a list of
|
||||
// new sigs. Every entry in `port_replacements` must name an output port
|
||||
// of root_cell, and the list must cover ALL of root_cell's output ports
|
||||
// (both verified via kernel/newcelltypes.h). For each (port, new_sig)
|
||||
// pair the original port signal is connected to new_sig at the module
|
||||
// level. All of root_cell's ports are then unset and the cell is
|
||||
// removed (asserted: no connections remain at the point of removal).
|
||||
// Src is auto-merged from root_cell + extras + merge_src_into into
|
||||
// every staged new cell and into merge_src_into.
|
||||
void patch_ports(Cell* root_cell,
|
||||
const std::vector<std::pair<IdString, SigSpec>>& port_replacements,
|
||||
const std::vector<Cell*>& extras = {},
|
||||
Cell* merge_src_into = nullptr);
|
||||
|
||||
// Flush staged cells_ / wires_ into the module without doing any
|
||||
// connect_incremental or gc. Each committed cell's src attribute is
|
||||
// pulled from `src_source` (typically the cell that's being expanded /
|
||||
// unmapped into the staged helpers, so source-location tracking carries
|
||||
// through transparently). Pass nullptr for src_source if the staged
|
||||
// helpers have no natural ancestor.
|
||||
// connect_incremental or port rewiring. Each committed cell's src
|
||||
// attribute is pulled from `src_source` (typically the cell that's
|
||||
// being expanded / unmapped into the staged helpers, so source-location
|
||||
// tracking carries through transparently). Pass nullptr for src_source
|
||||
// if the staged helpers have no natural ancestor.
|
||||
void commit_inheriting_src(Cell* src_source);
|
||||
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
|
||||
RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue