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analogdevices: update timing model

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Lofty 2025-10-01 20:13:29 +01:00
parent 9d98cf8864
commit 763c69b554
4 changed files with 168 additions and 425 deletions
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24
techlibs/analogdevices/arith_map.v
View file

@ -50,10 +50,18 @@ generate
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
if (i == 0) begin if (i == 0) begin
CRY4 carry4 wire INITCO;
CRY4INIT init
( (
.CYINIT(CI), .CYINIT(CI),
.CI (1'd0), .CO (INITCO)
);
CRY4 carry4
(
.CYINIT(1'd0),
.CI (INITCO),
.DI (GG[i*4 +: 4]), .DI (GG[i*4 +: 4]),
.S (S [i*4 +: 4]), .S (S [i*4 +: 4]),
.CO (C [i*4 +: 4]), .CO (C [i*4 +: 4]),
@ -130,10 +138,18 @@ module _80_analogdevices_alu (A, B, CI, BI, X, Y, CO);
genvar i; genvar i;
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
if (i == 0) begin if (i == 0) begin
CRY4 carry4 wire INITCO;
CRY4INIT init
( (
.CYINIT(CI), .CYINIT(CI),
.CI (1'd0), .CO (INITCO)
);
CRY4 carry4
(
.CYINIT(1'd0),
.CI (INITCO),
.DI (DI[i*4 +: 4]), .DI (DI[i*4 +: 4]),
.S (S [i*4 +: 4]), .S (S [i*4 +: 4]),
.O (O [i*4 +: 4]), .O (O [i*4 +: 4]),

565
techlibs/analogdevices/cells_sim.v
View file

@ -17,10 +17,6 @@
* *
*/ */
// See Analog Devices UG953 and UG474 for a description of the cell types below.
// http://www.analogdevices.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
// http://www.analogdevices.com/support/documentation/sw_manuals/analogdevices2014_4/ug953-vivado-7series-libraries.pdf
module VDD(output P); module VDD(output P);
assign P = 1; assign P = 1;
endmodule endmodule
@ -41,7 +37,7 @@ module INBUF(
parameter IOSTANDARD = "DEFAULT"; parameter IOSTANDARD = "DEFAULT";
assign O = I; assign O = I;
specify specify
(I => O) = 0; (I => O) = 22;
endspecify endspecify
endmodule endmodule
@ -66,7 +62,7 @@ module OUTBUF(
parameter SLEW = "SLOW"; parameter SLEW = "SLOW";
assign O = I; assign O = I;
specify specify
(I => O) = 0; (I => O) = 22;
endspecify endspecify
endmodule endmodule
@ -182,7 +178,7 @@ module INV(
); );
assign O = !I; assign O = !I;
specify specify
(I => O) = 127; (I => O) = 22;
endspecify endspecify
endmodule endmodule
@ -191,7 +187,7 @@ module LUT1(output O, input I0);
parameter [1:0] INIT = 0; parameter [1:0] INIT = 0;
assign O = I0 ? INIT[1] : INIT[0]; assign O = I0 ? INIT[1] : INIT[0];
specify specify
(I0 => O) = 127; (I0 => O) = 22;
endspecify endspecify
endmodule endmodule
@ -201,8 +197,8 @@ module LUT2(output O, input I0, I1);
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign O = I0 ? s1[1] : s1[0]; assign O = I0 ? s1[1] : s1[0];
specify specify
(I0 => O) = 238; (I0 => O) = 22;
(I1 => O) = 127; (I1 => O) = 22;
endspecify endspecify
endmodule endmodule
@ -213,13 +209,13 @@ module LUT3(output O, input I0, I1, I2);
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0]; assign O = I0 ? s1[1] : s1[0];
specify specify
(I0 => O) = 407; (I0 => O) = 22;
(I1 => O) = 238; (I1 => O) = 22;
(I2 => O) = 127; (I2 => O) = 22;
endspecify endspecify
endmodule endmodule
(* abc9_lut=3 *) (* abc9_lut=4 *)
module LUT4(output O, input I0, I1, I2, I3); module LUT4(output O, input I0, I1, I2, I3);
parameter [15:0] INIT = 0; parameter [15:0] INIT = 0;
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
@ -227,14 +223,14 @@ module LUT4(output O, input I0, I1, I2, I3);
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0]; assign O = I0 ? s1[1] : s1[0];
specify specify
(I0 => O) = 472; (I0 => O) = 22;
(I1 => O) = 407; (I1 => O) = 22;
(I2 => O) = 238; (I2 => O) = 22;
(I3 => O) = 127; (I3 => O) = 22;
endspecify endspecify
endmodule endmodule
(* abc9_lut=3 *) (* abc9_lut=5 *)
module LUT5(output O, input I0, I1, I2, I3, I4); module LUT5(output O, input I0, I1, I2, I3, I4);
parameter [31:0] INIT = 0; parameter [31:0] INIT = 0;
wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
@ -243,18 +239,15 @@ module LUT5(output O, input I0, I1, I2, I3, I4);
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0]; assign O = I0 ? s1[1] : s1[0];
specify specify
(I0 => O) = 631; (I0 => O) = 22;
(I1 => O) = 472; (I1 => O) = 22;
(I2 => O) = 407; (I2 => O) = 22;
(I3 => O) = 238; (I3 => O) = 22;
(I4 => O) = 127; (I4 => O) = 22;
endspecify endspecify
endmodule endmodule
// This is a placeholder for ABC9 to extract the area/delay (* abc9_lut=6 *)
// cost of 3-input LUTs and is not intended to be instantiated
(* abc9_lut=5 *)
module LUT6(output O, input I0, I1, I2, I3, I4, I5); module LUT6(output O, input I0, I1, I2, I3, I4, I5);
parameter [63:0] INIT = 0; parameter [63:0] INIT = 0;
wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
@ -264,12 +257,12 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5);
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0]; assign O = I0 ? s1[1] : s1[0];
specify specify
(I0 => O) = 642; (I0 => O) = 22;
(I1 => O) = 631; (I1 => O) = 22;
(I2 => O) = 472; (I2 => O) = 22;
(I3 => O) = 407; (I3 => O) = 22;
(I4 => O) = 238; (I4 => O) = 22;
(I5 => O) = 127; (I5 => O) = 22;
endspecify endspecify
endmodule endmodule
@ -291,37 +284,35 @@ endmodule
// This is a placeholder for ABC9 to extract the area/delay // This is a placeholder for ABC9 to extract the area/delay
// cost of 3-input LUTs and is not intended to be instantiated // cost of 3-input LUTs and is not intended to be instantiated
(* abc9_lut=10 *) (* abc9_lut=12 *)
module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6); module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
`ifndef __ICARUS__ `ifndef __ICARUS__
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867 (I0 => O) = 22 + 63 /* LUTMUX7.I1 */;
(I0 => O) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; (I1 => O) = 22 + 63 /* LUTMUX7.I1 */;
(I1 => O) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; (I2 => O) = 22 + 63 /* LUTMUX7.I1 */;
(I2 => O) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; (I3 => O) = 22 + 63 /* LUTMUX7.I1 */;
(I3 => O) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; (I4 => O) = 22 + 63 /* LUTMUX7.I1 */;
(I4 => O) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; (I5 => O) = 22 + 63 /* LUTMUX7.I1 */;
(I5 => O) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; (I6 => O) = 0 + 51 /* LUTMUX7.S */;
(I6 => O) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */;
endspecify endspecify
`endif `endif
endmodule endmodule
// This is a placeholder for ABC9 to extract the area/delay // This is a placeholder for ABC9 to extract the area/delay
// cost of 3-input LUTs and is not intended to be instantiated // cost of 3-input LUTs and is not intended to be instantiated
(* abc9_lut=20 *) (* abc9_lut=24 *)
module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7); module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
`ifndef __ICARUS__ `ifndef __ICARUS__
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L716 (I0 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */;
(I0 => O) = 642 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; (I1 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */;
(I1 => O) = 631 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; (I2 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */;
(I2 => O) = 472 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; (I3 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */;
(I3 => O) = 407 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; (I4 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */;
(I4 => O) = 238 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; (I5 => O) = 22 + 63 /* LUTMUX7.I1 */ + 48 /* LUTMUX8.I0 */;
(I5 => O) = 127 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; (I6 => O) = 0 + 51 /* LUTMUX7.S */ + 48 /* LUTMUX8.I0 */;
(I6 => O) = 0 + 296 /* to select F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */; (I7 => O) = 0 + 0 + 58 /* LUTMUX8.S */;
(I7 => O) = 0 + 0 + 273 /* to select F8MUX */ + 192 /* BMUX */;
endspecify endspecify
`endif `endif
endmodule endmodule
@ -330,10 +321,9 @@ endmodule
module LUTMUX7(output O, input I0, I1, S); module LUTMUX7(output O, input I0, I1, S);
assign O = S ? I1 : I0; assign O = S ? I1 : I0;
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L451-L453 (I0 => O) = 62;
(I0 => O) = 217; (I1 => O) = 63;
(I1 => O) = 223; (S => O) = 51;
(S => O) = 296;
endspecify endspecify
endmodule endmodule
@ -341,10 +331,9 @@ endmodule
module LUTMUX8(output O, input I0, I1, S); module LUTMUX8(output O, input I0, I1, S);
assign O = S ? I1 : I0; assign O = S ? I1 : I0;
specify specify
// Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L462-L464 (I0 => O) = 48;
(I0 => O) = 104; (I1 => O) = 46;
(I1 => O) = 94; (S => O) = 58;
(S => O) = 273;
endspecify endspecify
endmodule endmodule
@ -365,79 +354,65 @@ module CRY4(
assign CO[3] = S[3] ? CO[2] : DI[3]; assign CO[3] = S[3] ? CO[2] : DI[3];
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46 // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46
(CYINIT => O[0]) = 482; (S[0] => O[0]) = 39;
(S[0] => O[0]) = 223; (CI => O[0]) = 43;
(CI => O[0]) = 222; (DI[0] => O[1]) = 81;
(CYINIT => O[1]) = 598; (S[0] => O[1]) = 61;
(DI[0] => O[1]) = 407; (S[1] => O[1]) = 42;
(S[0] => O[1]) = 400; (CI => O[1]) = 50;
(S[1] => O[1]) = 205; (DI[0] => O[2]) = 98;
(CI => O[1]) = 334; (DI[1] => O[2]) = 95;
(CYINIT => O[2]) = 584; (S[0] => O[2]) = 70;
(DI[0] => O[2]) = 556; (S[1] => O[2]) = 75;
(DI[1] => O[2]) = 537; (S[2] => O[2]) = 48;
(S[0] => O[2]) = 523; (CI => O[2]) = 64;
(S[1] => O[2]) = 558; (DI[0] => O[3]) = 101;
(S[2] => O[2]) = 226; (DI[1] => O[3]) = 120;
(CI => O[2]) = 239; (DI[2] => O[3]) = 65;
(CYINIT => O[3]) = 642; (S[0] => O[3]) = 69;
(DI[0] => O[3]) = 615; (S[1] => O[3]) = 91;
(DI[1] => O[3]) = 596; (S[2] => O[3]) = 42;
(DI[2] => O[3]) = 438; (S[3] => O[3]) = 39;
(S[0] => O[3]) = 582; (CI => O[3]) = 84;
(S[1] => O[3]) = 618; (DI[0] => CO[0]) = 59;
(S[2] => O[3]) = 330; (S[0] => CO[0]) = 43;
(S[3] => O[3]) = 227; (CI => CO[0]) = 50;
(CI => O[3]) = 313; (DI[0] => CO[1]) = 87;
(CYINIT => CO[0]) = 536; (DI[1] => CO[1]) = 64;
(DI[0] => CO[0]) = 379; (S[0] => CO[1]) = 63;
(S[0] => CO[0]) = 340; (S[1] => CO[1]) = 51;
(CI => CO[0]) = 271; (CI => CO[1]) = 55;
(CYINIT => CO[1]) = 494; (DI[0] => CO[2]) = 103;
(DI[0] => CO[1]) = 465; (DI[1] => CO[2]) = 113;
(DI[1] => CO[1]) = 445; (DI[2] => CO[2]) = 58;
(S[0] => CO[1]) = 433; (S[0] => CO[2]) = 68;
(S[1] => CO[1]) = 469; (S[1] => CO[2]) = 79;
(CI => CO[1]) = 157; (S[2] => CO[2]) = 37;
(CYINIT => CO[2]) = 592; (CI => CO[2]) = 77;
(DI[0] => CO[2]) = 540; (DI[0] => CO[3]) = 93;
(DI[1] => CO[2]) = 520; (DI[1] => CO[3]) = 95;
(DI[2] => CO[2]) = 356; (DI[2] => CO[3]) = 84;
(S[0] => CO[2]) = 512; (DI[3] => CO[3]) = 72;
(S[1] => CO[2]) = 548; (S[0] => CO[3]) = 91;
(S[2] => CO[2]) = 292; (S[1] => CO[3]) = 97;
(CI => CO[2]) = 228; (S[2] => CO[3]) = 82;
(CYINIT => CO[3]) = 580; (S[3] => CO[3]) = 81;
(DI[0] => CO[3]) = 526; (CI => CO[3]) = 20;
(DI[1] => CO[3]) = 507;
(DI[2] => CO[3]) = 398;
(DI[3] => CO[3]) = 385;
(S[0] => CO[3]) = 508;
(S[1] => CO[3]) = 528;
(S[2] => CO[3]) = 378;
(S[3] => CO[3]) = 380;
(CI => CO[3]) = 114;
endspecify endspecify
endmodule endmodule
module CARRY8( (* abc9_box, lib_whitebox *)
output [7:0] CO, module CRY4INIT(
output [7:0] O, (* abc9_carry *)
input CI, output CO,
input CI_TOP, (* abc9_carry *)
input [7:0] DI, S input CYINIT
); );
parameter CARRY_TYPE = "SINGLE_CY8"; specify
wire CI4 = (CARRY_TYPE == "DUAL_CY4" ? CI_TOP : CO[3]); (CYINIT => CO) = 72;
assign O = S ^ {CO[6:4], CI4, CO[2:0], CI}; endspecify
assign CO[0] = S[0] ? CI : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1]; assign CO = CYINIT;
assign CO[2] = S[2] ? CO[1] : DI[2];
assign CO[3] = S[3] ? CO[2] : DI[3];
assign CO[4] = S[4] ? CI4 : DI[4];
assign CO[5] = S[5] ? CO[4] : DI[5];
assign CO[6] = S[6] ? CO[5] : DI[6];
assign CO[7] = S[7] ? CO[6] : DI[7];
endmodule endmodule
module ORCY (output O, input CI, I); module ORCY (output O, input CI, I);
@ -448,48 +423,26 @@ module MULT_AND (output LO, input I0, I1);
assign LO = I0 & I1; assign LO = I0 & I1;
endmodule endmodule
// Flip-flops and latches. // Flip-flops.
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
(* abc9_flop, lib_whitebox *) (* abc9_flop, lib_whitebox *)
module FFRE ( module FFRE (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C, input C,
input CE, input CE,
(* invertible_pin = "IS_D_INVERTED" *)
input D, input D,
(* invertible_pin = "IS_R_INVERTED" *)
input R input R
); );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
initial Q <= INIT; initial Q <= INIT;
generate always @(posedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
case (|IS_C_INVERTED)
1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase
endgenerate
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 $setup(D , posedge C, 31);
$setup(D , posedge C &&& CE && !IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported $setup(CE, posedge C, 122);
$setup(D , negedge C &&& CE && IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported $setup(R , posedge C, 128);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 if (R) (posedge C => (Q : 1'b0)) = 280;
$setup(CE, posedge C &&& !IS_C_INVERTED, 109); if (!R && CE) (posedge C => (Q : D)) = 280;
$setup(CE, negedge C &&& IS_C_INVERTED, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(R , posedge C &&& !IS_C_INVERTED, 404);
$setup(R , negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
if (!IS_C_INVERTED && R != IS_R_INVERTED) (posedge C => (Q : 1'b0)) = 303;
if ( IS_C_INVERTED && R != IS_R_INVERTED) (negedge C => (Q : 1'b0)) = 303;
if (!IS_C_INVERTED && R == IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && R == IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify endspecify
endmodule endmodule
@ -506,59 +459,34 @@ module FFRE_N (
initial Q <= INIT; initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 $setup(D , negedge C, 31);
$setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported $setup(CE, negedge C, 122);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(R , negedge C, 128);
$setup(CE, negedge C, 109); if (R) (negedge C => (Q : 1'b0)) = 280;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 if (!R && CE) (negedge C => (Q : D)) = 280;
$setup(R , negedge C, 404); // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
if (R) (negedge C => (Q : 1'b0)) = 303;
if (!R && CE) (negedge C => (Q : D)) = 303;
endspecify endspecify
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module FFSE ( module FFSE (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C, input C,
input CE, input CE,
(* invertible_pin = "IS_D_INVERTED" *)
input D, input D,
(* invertible_pin = "IS_S_INVERTED" *)
input S input S
); );
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT; initial Q <= INIT;
generate always @(posedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
case (|IS_C_INVERTED)
1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase
endgenerate
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 $setup(D , posedge C, 31);
$setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported $setup(CE, posedge C, 122);
$setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported $setup(S , posedge C, 128);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 if (S) (negedge C => (Q : 1'b1)) = 280;
$setup(CE, posedge C &&& !IS_C_INVERTED, 109); if (!S && CE) (posedge C => (Q : D)) = 280;
$setup(CE, negedge C &&& IS_C_INVERTED, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(S , posedge C &&& !IS_C_INVERTED, 404);
$setup(S , negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
if (!IS_C_INVERTED && S != IS_S_INVERTED) (posedge C => (Q : 1'b1)) = 303;
if ( IS_C_INVERTED && S != IS_S_INVERTED) (negedge C => (Q : 1'b1)) = 303;
if (!IS_C_INVERTED && S == IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && S == IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify endspecify
endmodule endmodule
(* abc9_flop, lib_whitebox *)
module FFSE_N ( module FFSE_N (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
@ -571,68 +499,32 @@ module FFSE_N (
initial Q <= INIT; initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 $setup(D , negedge C, 31);
$setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported $setup(CE, negedge C, 122);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(S , negedge C, 128);
$setup(CE, negedge C, 109); if (S) (negedge C => (Q : 1'b1)) = 280;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 if (!S && CE) (negedge C => (Q : D)) = 280;
$setup(S , negedge C, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
if (S) (negedge C => (Q : 1'b1)) = 303;
if (!S && CE) (negedge C => (Q : D)) = 303;
endspecify endspecify
endmodule endmodule
(* abc9_box, lib_whitebox *)
module FFCE ( module FFCE (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C, input C,
input CE, input CE,
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR, input CLR,
(* invertible_pin = "IS_D_INVERTED" *)
input D input D
); );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
initial Q <= INIT; initial Q <= INIT;
generate always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D;
case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase
endgenerate
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 $setup(D , posedge C, 31);
$setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported $setup(CE , posedge C, 122);
$setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported if (!CLR && CE) (posedge C => (Q : D)) = 280;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE , posedge C &&& !IS_C_INVERTED, 109);
$setup(CE , negedge C &&& IS_C_INVERTED, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(CLR, posedge C &&& !IS_C_INVERTED, 404);
$setup(CLR, negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
`ifndef YOSYS
if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764;
if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764;
`else
if (IS_CLR_INVERTED != CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify endspecify
endmodule endmodule
(* abc9_box, lib_whitebox *)
module FFCE_N ( module FFCE_N (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
@ -645,213 +537,48 @@ module FFCE_N (
initial Q <= INIT; initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 $setup(D , negedge C, 31);
$setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported $setup(CE , negedge C, 122);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 if (!CLR && CE) (negedge C => (Q : D)) = 280;
$setup(CE , negedge C, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(CLR, negedge C, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
`ifndef YOSYS
(posedge CLR => (Q : 1'b0)) = 764;
`else
if (CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!CLR && CE) (negedge C => (Q : D)) = 303;
endspecify endspecify
endmodule endmodule
(* abc9_box, lib_whitebox *)
module FFPE ( module FFPE (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C, input C,
input CE, input CE,
(* invertible_pin = "IS_D_INVERTED" *) input PRE,
input D, input D
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE
); );
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT; initial Q <= INIT;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D;
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase
endgenerate
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 $setup(D , posedge C, 31);
$setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported $setup(CE , posedge C, 122);
$setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported if (!PRE && CE) (posedge C => (Q : D)) = 291;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE , posedge C &&& !IS_C_INVERTED, 109);
$setup(CE , negedge C &&& IS_C_INVERTED, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(PRE, posedge C &&& !IS_C_INVERTED, 404);
$setup(PRE, negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
`ifndef YOSYS
if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764;
if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764;
`else
if (IS_PRE_INVERTED != PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify endspecify
endmodule endmodule
(* abc9_box, lib_whitebox *)
module FFPE_N ( module FFPE_N (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
input C, input C,
input CE, input CE,
input D, input PRE,
input PRE input D
); );
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q <= INIT; initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
specify specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 $setup(D , negedge C, 31);
$setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported $setup(CE , negedge C, 122);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 if (!PRE && CE) (negedge C => (Q : D)) = 291;
$setup(CE , negedge C, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(PRE, negedge C, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
`ifndef YOSYS
(posedge PRE => (Q : 1'b1)) = 764;
`else
if (PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!PRE && CE) (negedge C => (Q : D)) = 303;
endspecify endspecify
endmodule endmodule
module FFCPE (
output wire Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input CE,
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR,
input D,
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
wire c = C ^ IS_C_INVERTED;
wire clr = CLR ^ IS_CLR_INVERTED;
wire pre = PRE ^ IS_PRE_INVERTED;
// Hacky model to avoid simulation-synthesis mismatches.
reg qc, qp, qs;
initial qc = INIT;
initial qp = INIT;
initial qs = 0;
always @(posedge c, posedge clr) begin
if (clr)
qc <= 0;
else if (CE)
qc <= D;
end
always @(posedge c, posedge pre) begin
if (pre)
qp <= 1;
else if (CE)
qp <= D;
end
always @* begin
if (clr)
qs <= 0;
else if (pre)
qs <= 1;
end
assign Q = qs ? qp : qc;
endmodule
module FFCPE_N (
output wire Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input CE,
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR,
input D,
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
wire c = C ^ IS_C_INVERTED;
wire clr = CLR ^ IS_CLR_INVERTED;
wire pre = PRE ^ IS_PRE_INVERTED;
// Hacky model to avoid simulation-synthesis mismatches.
reg qc, qp, qs;
initial qc = INIT;
initial qp = INIT;
initial qs = 0;
always @(negedge c, posedge clr) begin
if (clr)
qc <= 0;
else if (CE)
qc <= D;
end
always @(negedge c, posedge pre) begin
if (pre)
qp <= 1;
else if (CE)
qp <= D;
end
always @* begin
if (clr)
qs <= 0;
else if (pre)
qs <= 1;
end
assign Q = qs ? qp : qc;
endmodule
module AND2B1L (
output O,
input DI,
(* invertible_pin = "IS_SRI_INVERTED" *)
input SRI
);
parameter [0:0] IS_SRI_INVERTED = 1'b0;
assign O = DI & ~(SRI ^ IS_SRI_INVERTED);
endmodule
module OR2L (
output O,
input DI,
(* invertible_pin = "IS_SRI_INVERTED" *)
input SRI
);
parameter [0:0] IS_SRI_INVERTED = 1'b0;
assign O = DI | (SRI ^ IS_SRI_INVERTED);
endmodule
// LUTRAM. // LUTRAM.
// Single port. // Single port.

2
techlibs/analogdevices/lut_map.v
View file

@ -72,7 +72,7 @@ module \$lut (A, Y);
wire f0, f1; wire f0, f1;
\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0)); \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1)); \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
LUTMUX8 mux8(.I0(f0), .I1(f1), .S(A[7]), .O(Y)); LUTMUX8 mux8 (.I0(f0), .I1(f1), .S(A[7]), .O(Y));
end else begin end else begin
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
end end

2
techlibs/analogdevices/synth_analogdevices.cc
View file

@ -464,7 +464,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
abc_opts += " -dff"; abc_opts += " -dff";
if (retime) if (retime)
abc_opts += " -D 1"; abc_opts += " -D 1";
run("abc" + abc_opts); run("abc -dress" + abc_opts);
} }
run("clean"); run("clean");