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analogdevices: update timing model

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Lofty 2025-10-01 20:13:29 +01:00
parent 9d98cf8864
commit 763c69b554
4 changed files with 168 additions and 425 deletions
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24
techlibs/analogdevices/arith_map.v
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@ -50,10 +50,18 @@ generate
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
if (i == 0) begin
CRY4 carry4
wire INITCO;
CRY4INIT init
(
.CYINIT(CI),
.CI (1'd0),
.CO (INITCO)
);
CRY4 carry4
(
.CYINIT(1'd0),
.CI (INITCO),
.DI (GG[i*4 +: 4]),
.S (S [i*4 +: 4]),
.CO (C [i*4 +: 4]),
@ -130,10 +138,18 @@ module _80_analogdevices_alu (A, B, CI, BI, X, Y, CO);
genvar i;
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
if (i == 0) begin
CRY4 carry4
wire INITCO;
CRY4INIT init
(
.CYINIT(CI),
.CI (1'd0),
.CO (INITCO)
);
CRY4 carry4
(
.CYINIT(1'd0),
.CI (INITCO),
.DI (DI[i*4 +: 4]),
.S (S [i*4 +: 4]),
.O (O [i*4 +: 4]),