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ecp5: do not map FFRAM if explicitly requested otherwise.

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This commit is contained in:
whitequark 2020-01-01 10:11:35 +00:00
parent ebee746ad2
commit 763401fc82
2 changed files with 65 additions and 17 deletions
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4
techlibs/ecp5/synth_ecp5.cc
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@ -279,7 +279,9 @@ struct SynthEcp5Pass : public ScriptPass
if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block "
"-attr syn_ramstyle=auto -attr syn_ramstyle=registers "
"-attr syn_romstyle=auto -attr syn_romstyle=logic");
run("opt -undriven -fine");
}

78
tests/arch/ecp5/memories.ys
View file

@ -50,15 +50,25 @@ design -reset; read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
setattr -set syn_romstyle "ebr" m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:PDPW16KD # requested BROM but this is a RAM
select -assert-count 180 t:TRELLIS_FF
select -assert-count 1 t:$mem # requested BROM but this is a RAM
design -reset; read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
setattr -set rom_block 1 m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:PDPW16KD # requested BROM but this is a RAM
select -assert-count 180 t:TRELLIS_FF
select -assert-count 1 t:$mem # requested BROM but this is a RAM
design -reset; read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
setattr -set syn_ramstyle "block_ram" m:memory
synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
design -reset; read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
setattr -set ram_block 1 m:memory
synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
# RAM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
@ -131,15 +141,25 @@ design -reset; read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
setattr -set syn_romstyle "ebr" m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:DP16KD # requested BROM but this is a RAM
select -assert-count 90 t:TRELLIS_FF
select -assert-count 1 t:$mem # requested BROM but this is a RAM
design -reset; read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
setattr -set rom_block 1 m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:DP16KD # requested BROM but this is a RAM
select -assert-count 90 t:TRELLIS_FF
select -assert-count 1 t:$mem # requested BROM but this is a RAM
design -reset; read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
setattr -set syn_ramstyle "block_ram" m:memory
synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
design -reset; read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
setattr -set ram_block 1 m:memory
synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
# RAM bits <= 64; Data width <= 4; Address width <= 4: -> DPR16X4
@ -170,6 +190,12 @@ synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
select -assert-count 68 t:TRELLIS_FF
design -reset; read_verilog ../common/blockram.v
chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
setattr -set syn_ramstyle "distributed" m:memory
synth_ecp5 -top sync_ram_sdp -nolutram; cd sync_ram_sdp
select -assert-count 1 t:$mem # requested LUTRAM but LUTRAM is disabled
# ================================ ROM ================================
# ROM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
@ -217,15 +243,25 @@ design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
setattr -set syn_ramstyle "block_ram" m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:PDPW16KD # requested BRAM but this is a ROM
select -assert-min 18 t:LUT4
select -assert-count 1 t:$mem # requested BRAM but this is a ROM
design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
setattr -set ram_block 1 m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:PDPW16KD # requested BRAM but this is a ROM
select -assert-min 18 t:LUT4
select -assert-count 1 t:$mem # requested BRAM but this is a ROM
design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
setattr -set syn_ramstyle "block_rom" m:memory
synth_ecp5 -top sync_rom -nobram; cd sync_rom
select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
setattr -set rom_block 1 m:memory
synth_ecp5 -top sync_rom -nobram; cd sync_rom
select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
# ROM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
@ -273,12 +309,22 @@ design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
setattr -set syn_ramstyle "block_ram" m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:DP16KD # requested BRAM but this is a ROM
select -assert-min 9 t:LUT4
select -assert-count 1 t:$mem # requested BRAM but this is a ROM
design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
setattr -set ram_block 1 m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:DP16KD # requested BRAM but this is a ROM
select -assert-min 9 t:LUT4
select -assert-count 1 t:$mem # requested BRAM but this is a ROM
design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
setattr -set syn_ramstyle "block_rom" m:memory
synth_ecp5 -top sync_rom -nobram; cd sync_rom
select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
design -reset; read_verilog ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
setattr -set rom_block 1 m:memory
synth_ecp5 -top sync_rom -nobram; cd sync_rom
select -assert-count 1 t:$mem # requested BROM but BRAM is disabled