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add separate module test

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Rahul Bhagwat 2025-08-03 23:48:33 -04:00
parent b776283d79
commit 761015b23e
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4 changed files with 54 additions and 3 deletions
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13
tests/verilog/package_import_separate.sv Normal file
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@ -0,0 +1,13 @@
package config_pkg;
localparam integer
DATA_WIDTH = 8,
ADDR_WIDTH = 4;
localparam logic [2:0]
IDLE = 3'b000,
START = 3'b001,
DATA = 3'b010,
ODD_PARITY = 3'b011,
STOP = 3'b100,
DONE = 3'b101;
endpackage