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proc_dff: Fix emitted FF when a register is not assigned in async reset

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Fixes #2619.
This commit is contained in:
Marcelina Kościelnicka 2021-03-06 03:59:03 +01:00
parent bc717abad2
commit 760284033d
2 changed files with 27 additions and 0 deletions
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23
tests/proc/bug2619.ys Normal file
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@ -0,0 +1,23 @@
read_verilog << EOT
module top(...);
input D1, D2, R, CLK;
output reg Q1, Q2;
always @(posedge CLK, posedge R) begin
Q1 <= 0;
if (!R) begin
Q1 <= D1;
Q2 <= D2;
end
end
endmodule
EOT
proc
opt
select -assert-count 1 t:$adff
select -assert-count 1 t:$dffe