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Merge pull request #1703 from YosysHQ/eddie/specify_improve

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Improve specify parser
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Eddie Hung 2020-02-21 09:15:17 -08:00 • committed by GitHub
commit 760096e8d2
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8 changed files with 170 additions and 52 deletions
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12
backends/verilog/verilog_backend.cc
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@ -1417,11 +1417,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
decimal = 1;
f << ", ";
dump_const(f, cell->getParam("\\T_LIMIT"));
dump_const(f, cell->getParam("\\T_LIMIT_MIN"));
f << ": ";
dump_const(f, cell->getParam("\\T_LIMIT_TYP"));
f << ": ";
dump_const(f, cell->getParam("\\T_LIMIT_MAX"));
if (spec_type == "$setuphold" || spec_type == "$recrem" || spec_type == "$fullskew") {
f << ", ";
dump_const(f, cell->getParam("\\T_LIMIT2"));
dump_const(f, cell->getParam("\\T_LIMIT2_MIN"));
f << ": ";
dump_const(f, cell->getParam("\\T_LIMIT2_TYP"));
f << ": ";
dump_const(f, cell->getParam("\\T_LIMIT2_MAX"));
}
f << ");\n";