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https://github.com/YosysHQ/yosys
synced 2026-05-21 01:19:39 +00:00
Convert RTLIL::unescape_id of IdString to unescape()
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parent
8bbc3c359c
commit
75dcbe03c6
35 changed files with 636 additions and 114 deletions
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@ -71,10 +71,10 @@ struct LibertyStubber {
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std::sort(sorted_ports.begin(), sorted_ports.end(), cmp);
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std::string clock_pin_name = "";
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for (auto x : sorted_ports) {
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std::string port_name = RTLIL::unescape_id(x);
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std::string port_name = x.unescape();
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bool is_input = base_type.inputs.count(x);
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bool is_output = base_type.outputs.count(x);
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f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n";
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f << "\t\tpin (" << x.unescape() << ") {\n";
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if (is_input && !is_output) {
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i.item("direction", "input");
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} else if (!is_input && is_output) {
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@ -132,7 +132,7 @@ struct LibertyStubber {
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for (auto x : derived->ports) {
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bool is_input = base_type.inputs.count(x);
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bool is_output = base_type.outputs.count(x);
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f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n";
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f << "\t\tpin (" << x.unescape() << ") {\n";
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if (is_input && !is_output) {
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f << "\t\t\tdirection : input;\n";
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} else if (!is_input && is_output) {
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@ -244,7 +244,7 @@ struct PortarcsPass : Pass {
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if (draw_mode) {
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auto bit_str = [](SigBit bit) {
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return stringf("%s%d", RTLIL::unescape_id(bit.wire->name.str()), bit.offset);
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return stringf("%s%d", bit.wire, bit.offset);
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};
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std::vector<std::string> headings;
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@ -621,7 +621,7 @@ struct RenamePass : public Pass {
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RTLIL::Module *module_to_rename = nullptr;
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for (auto module : design->modules())
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if (module->name == from_name || RTLIL::unescape_id(module->name) == from_name) {
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if (module->name == from_name || module->name.unescape() == from_name) {
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module_to_rename = module;
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break;
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}
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@ -549,7 +549,7 @@ struct ShowWorker
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net_conn_map[node].color = nextColor(sig, net_conn_map[node].color);
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}
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std::string proc_src = RTLIL::unescape_id(proc->name);
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std::string proc_src = proc->name.unescape();
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if (proc->attributes.count(ID::src) > 0)
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proc_src = proc->attributes.at(ID::src).decode_string();
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fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc->name.str()), proc_src.c_str(), findColor(proc->name).c_str());
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@ -227,7 +227,7 @@ struct WrapcellPass : Pass {
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if (!unused_outputs.empty()) {
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context.unused_outputs += "_unused";
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for (auto chunk : collect_chunks(unused_outputs))
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context.unused_outputs += "_" + RTLIL::unescape_id(chunk.format(cell));
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context.unused_outputs += "_" + chunk.format(cell).unescape();
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}
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std::optional<std::string> unescaped_name = format_with_params(name_fmt, cell->parameters, context);
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